Cyclone II FPGA Overview
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This training module will overview the Major Features and Design Capabilities of the Cyclone II FPGAs
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Cyclone II FPGA Overview
- 5. Altera product lineup High-end FPGAs with transceiver options CPLDs ASICs Low-cost FPGAs Design software Intellectual property (IP) Development kits Programmable logic solutions for all your needs Low-cost protocol-optimized FPGAs Embedded soft-core processors
- 8. Cyclone II Family Overview Note: All Densities Will be Offered in All Speed Grades (-6, -7, -8). -6 is the Fastest Speed Grade. Device Logic Elements M4K Memory Blocks Total Memory Bits 18x18 Embedded Multipliers PLLs Maximum User I/O Pins EP2C5 4,608 26 119,808 13 2 142 EP2C8 8,256 36 165,888 18 2 182 EP2C20 18,752 52 239,616 26 4 315 EP2C35 33,216 105 483,840 35 4 475 EP2C50 50,528 129 594,432 86 4 450 EP2C70 68,416 250 1,152,000 150 4 622
- 9. Cyclone II Packaging & User I/O Denotes Vertical Migration Support Note: (1) This device will be supported in the Quartus ® II version 5.0 software. (2) This device offers 299 user I/Os when vertical migration is enabled with the EP2C35. The 16 user I/Os in the EP2C20F484 become power and ground pins in the EP2C35F484 to support the core. Device 144-Pin TQFP 0.5 mm 22 x 22 208-Pin PQFP 0.5 mm 30.6 x30.6 256-Pin FBGA 1.0 mm 17 x 17 484-Pin FBGA 1.0 mm 23 x 23 672-Pin FBGA 1.0 mm 27 x 27 896-Pin FBGA 1.0 mm 31 x 31 EP2C5 89 142 158 (1) EP2C8 85 138 182 EP2C20 152 315 (2) EP2C35 322 475 EP2C50 294 450 EP2C70 422 622
- 11. Soft-Core Processor Available Programmable Logic Available Programmable Logic (1) Based on the Nios II fast core. (2) Based on the Nios II economy core. Device EP1C20 EP2C20 Performance 50 DMIPs 100 DMIPs (1) Logic Element Usage 1,200 LEs (Nios) 550 LEs (Nios II) (2) % of Device 6% 3% Cost of Nios $1.20 (Nios) $0.35 (Nios II)
- 13. EP2C35 Device Floorplan Logic Array M4K Memory Blocks Embedded Multipliers Phase-Locked Loops Side I/O Elements with Support for PCI/PCI-X & Memory Interfaces Top & Bottom I/O Elements with Support for Memory Interfaces
- 14. Cyclone II LAB Structure Cyclone II Logic Array Block (LAB) LAB-Wide Control Block 0 LUT 7 LUT 8 LUT 15 LUT 1 LUT 6 LUT 9 LUT 14 LUT 2 LUT 5 LUT 10 LUT 13 LUT 3 LUT 4 LUT 11 LUT 12 LUT
- 15. Cyclone II Logic Element LUT In1 In2 In3 In4 Carry In0 Carry In1 Carry Out0 Carry Out1 LUT Chain Register Chain General Routing Local Routing General Routing Register Chain Clock REG
- 16. Embedded Multiplier Details 18 Sign_X 18 X Y Sign_Y Input Registers 36 Clock Clear 36 Output Registers Note: Fastest Speed Grade with Registers Activated in 18x18 or 9x9 Mode 250-MHz Performance
- 18. External Memory Interface Summary Optimized in Dedicated Circuitry Note: New Standards Highlighted in Italics Memory Technology I/O Standard Bus Width Maximum Clock Speed Maximum Data Rate SDR SDRAM LVTTL 72 bits 167 MHz 167 Mbps DDR SDRAM SSTL-2 Class I SSTL-2 Class II 72 bits 72 bits 167 MHz 133 MHz 333 Mbps 266 Mbps DDR2 SDRAM SSTL-18 Class I SSTL-18 Class II 72 bits 72 bits 167 MHz 125 MHz 333 Mbps 250 Mbps QDRII SRAM HSTL 1.5V Class I HSTL 1.5V Class II 36 bits 36 bits 167 MHz 100 MHz 667 Mbps 400 Mbps
- 20. I/O Standards Summary Standard Target Performance Typical Applications Differential I/O Standards LVDS (Rx / Tx) 805 Mbps / 622 Mbps Chip-to-Chip RSDS, mini-LVDS 170 Mbps Chip-to-Chip Differential HSTL 167 MHz Memory Differential SSTL 167 MHz Memory LVPECL 150 MHz Clocks Single-Ended I/O Standards 3.3-V/2.5-V/1.8-V LVTTL 167 MHz General Purpose 3.3-V/2.5-V/1.8-V/1.5-V LVCMOS 167 MHz General Purpose SSTL-2 Class I / Class II 167 MHz / 133 MHz DDR Memory SSTL-18 Class I / Class II 167 MHz / 125 MHz DDR2 Memory 1.8-V HSTL Class I / Class II 167 MHz / 100 MHz Memory 1.5-V HSTL Class I / Class II 167 MHz / 100 MHz QDRII Memory 3.3-V PCI 66 MHz PC, Embedded 3.3-V PCI-X 100 MHz PC, Embedded
- 21. Single-Ended I/O Standards I/O Standard Typical Application Global Clock Inputs, I/O Inputs & I/O Outputs Top & Bottom Sides LVTTL/LVCMOS (1.8, 2.5, 3.3 V) General Purpose LVCMOS 1.5 V General Purpose, PCI Express PIPE SSTL-2.5 V Class I Memory SSTL-2.5 V Class II Memory SSTL-1.8 V Class I Memory SSTL-1.8 V Class II Memory HSTL-1.8 V Class I Memory HSTL-1.8 V Class II Memory HSTL-1.5 V Class I Memory HSTL-1.5 V Class II Memory PCI/PCI-X PC, Embedded
- 22. Differential I/O Standards I/O Standard Global Clock Inputs I/O Inputs I/O Outputs Top & Bottom Sides Top & Bottom Sides Top & Bottom Sides SSTL-2.5 V Class I SSTL-2.5 V Class II SSTL-1.8 V Class I SSTL-1.8 V Class II HSTL-1.8 V Class I HSTL-1.8 V Class II HSTL-1.5 V Class I HSTL-1.5 V Class II LVDS Mini LVDS RSDS LVPECL
- 23. I/O Element Structure Pin Output Enable Data Out Reg Output Clock Clock Data In Reg Data In Comb Data Out Comb REG REG REG
- 24. Programmable Drive Strength I/O Standard IOH/IOL Current Strength Setting (mA) LVTTL/LVCMOS (3.3 V) 4, 8, 12, 16, 20, 24 LVTTL/LVCMOS (2.5 V) 4, 8, 12, 16 LVTTL/LVCMOS (1.8 V) 2, 4, 6, 8, 10, 12 LVCMOS 1.5 V 2, 4, 6, 8 SSTL-2 Class I 8, 12 SSTL-2 Class II 16, 20, 24 SSTL-18 Class I 4, 6, 8, 10, 12 SSTL-18 Class II 8, 16, 18 HSTL-18 Class I 4, 6, 8, 10, 12 HSTL-18 Class II 16, 18, 20 HSTL-15 Class I 4, 6, 8, 10, 12 HSTL-15 Class II 16
- 26. I/O Bank Numbers & Locations EP2C5 to EP2C8 2 1 4 3 EP2C20 to EP2C70 3 4 8 7 2 1 5 6
- 27. PLL Parameters & Locations Cyclone II 3 2 1 4 PLL EP2C5 EP2C8 EP2C20 EP2C35 EP2C50 EP2C70 1 2 3 4 Parameter Cyclone II PLL Input Frequency Range 11 to 311 MHz Output Frequency Range 10 to 402.5 MHz Time to Lock from Power up 1 ms VCO Operating Range 300 MHz to 1 GHz
- 28. Altera Serial Configuration Device Family Details Notes: 1. EPCS1 & EPCS4 Devices Offered in 8-Pin SOIC Package. 2. EPCS16 & EPCS64 Devices Offered in 16-Pin SOIC Package Availability Availability EPCS1 EPCS4 EPCS16 EPCS64 1 Mbits 4 Mbits 16 Mbits 64 Mbits Configuration Device Capacity EP2C5 EP2C20 or Smaller All Cyclone II Devices All Cyclone II Devices Suitable Target Devices Now Now Now Now
- 29. Configuration File Size Estimates Note: All Values in Table Are Estimates & Subject to Change Cyclone II Device POF Size in Bits (Uncompressed) Approximate Configuration Times Active Serial (20 MHz) Active Serial (40 MHz) Passive Serial (100 MHz) EP2C5 1,265,792 35 ms 17 ms 7 ms EP2C8 1,983,536 63 ms 31 ms 13 ms EP2C20 3,892,496 144 ms 72 ms 29 ms EP2C35 6,858,656 255 ms 128 ms 51 ms EP2C50 9,963,392 389 ms 194 ms 78 ms EP2C70 14,319,216 527 ms 263 ms 105 ms
Notes de l'éditeur
- This is a training module for the Altera Cyclone II FPGA
- Welcome to this module on the Cyclone II family FPGA from Altera. The module overviews the major features of the Cyclone II family FPGA.
- Programmable logic is loosely defined as a device with configurable logic and flip-flops linked together with programmable resources that control the interconnections. User-programmable memory cells control and define the function that the logic performs and how the various logic functions are interconnected. Thus a wide range of sequential circuits can be implemented on a low-cost PLD. Though various devices use different architectures, all are based on this fundamental idea.
- FPGAs have gained rapid acceptance over the past decade because users can apply them to a wide range of applications: random logic, integrating multiple SPLDs, device controllers, communication encoding and filtering, small- to medium-size systems with SRAM blocks, and many more. Another interesting FPGA application is prototyping designs to be implemented in gate arrays by using one or more large FPGAs . An application only beginning development is the use of FPGAs as custom computing machines. This involves using the programmable parts to execute software, rather than compiling the software for execution on a regular CPU.
- Altera understands programmable devices are part of a bigger picture, and that true design success requires an array of other tools. To that end, Altera complements the complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs) with sophisticated software tools, pre-verified and configurable intellectual property (IP) cores, a soft-core processor – Nios II, development kits, and reference designs. Our comprehensive solution portfolios result in a faster, simplified design process and, in turn, faster time to market and lower development costs. With Altera® solutions, you can undertake your design, confident that you’ll be able to meet your unique application design goals.
- Following the immensely successful first-generation Cyclone® device family, Altera® Cyclone II FPGAs extend the low-cost FPGA density range to 68,416 logic elements (LEs) and provide up to 622 usable I/O pins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs are manufactured on 300-mm wafers using TSMC's 90-nm process to ensure rapid availability and low cost. By minimizing silicon area, Cyclone II devices can support complex digital systems on a single chip at a cost that rivals that of ASICs. Altera’s low-cost FPGAs—Cyclone II FPGAs, offer high performance and the low power consumption.
- Altera Cyclone II FPGAs extend the low-cost FPGA density range to 68,416 logic elements (LEs) and provide up to 622 usable I/O pins and up to 1.1 Mbits of embedded memory. Embedded multiplier block can implement up to either two 9 × 9-bit multipliers, or one 18 × 18-bit multiplier with up to 250-MHz performance. Embedded multipliers are arranged in columns across the device. Cyclone II devices support a broad range of external memory interfaces, such as SDR SDRAM, DDR SDRAM, DDR2 SDRAM, and QDRII SRAM. Dedicated clock delay control circuitry allows Cyclone II devices to interface with an external memory device at clock speeds up to 167 MHz/333 Mbps for DDR and DDR2 SDRAM devices and 167 MHz/667 Mbps for QDRII SRAM devices. Each Cyclone II device has up to four PLLs, supporting advanced capabilities such as clock switchover and programmable switchover. These PLLs offer clock multiplication and division, phase shifting, and programmable duty cycle and can be used to minimize clock delay and clock skew, and to reduce or adjust clock-to-out and set-up times.
- Altera® Cyclone II FPGAs extend the low-cost FPGA density range to 68,416 logic elements (LEs) and provide up to 622 usable I/O pins and up to 1.1 Mbits of embedded memory. Cyclone II devices include a powerful FPGA feature set optimized for low-cost applications including a wide range of density, memory, embedded multiplier, and packaging options. Cyclone II devices support a wide range of common external memory interfaces and I/O protocols required in low-cost applications.
- Vertical migration means that you can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. Cyclone II devices support vertical migration within the same package (for example, you can migrate between the EP2C35, EPC50, and EP2C70 devices in the 672-pin FineLine BGA package).
- Cyclone II devices support the Nios II embedded processor which allows to implement custom-fit embedded processing solutions. Cyclone II devices can also expand the peripheral set, memory, I/O, or performance of embedded processors. Single or multiple Nios II embedded processors can be designed into a Cyclone II device to provide additional co-processing power or even replace existing embedded processors in your system. Using Cyclone II and Nios II together allow for low-cost, high-performance embedded processing solutions, which allow you to extend your product's life cycle and improve time to market over standard product solutions.
- Nios and Nios II are the Soft Processor IP solutions from Altera for Embedded Applications. The table demonstrates the resource utilization or Logic Element usage summary for Nios and Nios II Embedded Processor within Cyclone II FPGAs. Nios II processor adds the advantage in better performance with less silicon utilization and comparatively low Cost.
- Altera’s Quartus II Design Software supports all the Cyclone II family Devices. Quartus II software has full integrity with advanced tool Such as SOPC Builder and DSP Builder for Embedded and DSP Applications respectively.
- Cyclone® II devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between logic array blocks (LABs), embedded memory blocks, and embedded multipliers.
- The logic array consists of LABs, with 16 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. Cyclone II devices range in density from 4,608 to 68,416 LEs. Each LAB consists of 16 Les, LAB control signals, LE carry chains, Register chains, and Local interconnect.
- The smallest unit of logic in the Cyclone II architecture, the LE, is compact and provides advanced features with efficient logic utilization. Each LE features a four-input look-up table (LUT), which is a function generator that can implement any function of four variables, a programmable register, a carry chain connection, a register chain connection, the ability to drive all types of interconnects: local, row, column, register chain, and direct link interconnects, support for register packing, and support for register feedback.
- Cyclone II devices have embedded multiplier blocks optimized for multiplier-intensive digital signal processing (DSP) functions, such as finite impulse response (FIR) filters, fast Fourier transform (FFT) functions, and discrete cosine transform (DCT) functions. The embedded multiplier consists of multiplier block, input and output registers, input and output interfaces. Each Cyclone II device has one to three columns of embedded multipliers that efficiently implement multiplication functions.
- Embedded multipliers can operate at up to 250 MHz (for the fastest speed grade) for 18 × 18 and 9 × 9 multiplications when using both input and output registers. An embedded multiplier can be configured to support a single 18 × 18 multiplier for operand widths up to 18 bits. All 18-bit multiplier inputs and results can be registered independently. The multiplier operands can accept signed integers, unsigned integers, or a combination of both. An embedded multiplier can be configured to support two 9 × 9 independent multipliers for operand widths up to 9-bits. Both 9-bit multiplier inputs and results can be registered independently. The multiplier operands can accept signed integers, unsigned integers or a combination of both.
- Cyclone® II devices support a broad range of external memory interfaces such as SDR SDRAM, DDR SDRAM, DDR2 SDRAM, and QDRII SRAM. Dedicated clock delay control circuitry allows Cyclone II devices to interface with an external memory device at clock speeds up to 167 MHz/333 Mbps for DDR and DDR2 SDRAM devices and 167 MHz/667 Mbps for QDRII SRAM devices. The easiest way to interface to external memory devices is by using one of the Altera® external memory IP cores, such as DDR2 SDRAM Controller MegaCore® Function, DDR SDRAM Controller MegaCore Function, QDRII SRAM Controller MegaCore Function and OpenCore® Plus evaluations of these cores are available for free to Quartus® II Web Edition software users.
- The Cyclone II embedded memory consists of columns of M4K memory blocks. The M4K memory blocks include input registers that synchronize writes and output registers to pipeline designs and improve system performance. The output registers can be bypassed, but input registers cannot. Each M4K block can implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and first-in first-out (FIFO) buffers.
- The proliferation of I/O standards and the need for improved I/O performance have made it critical that low-cost devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL-18, SSTL-2, and LVDS compatibility allow Cyclone® II devices to connect to other devices on the same printed circuit board (PCB) that may require different operating and I/O voltages. With these aspects of implementation easily manipulated using the Altera® Quartus® II software, the Cyclone II device family allows you to use low cost FPGAs while keeping pace with increasing design complexity.
- Cyclone II devices support single-ended I/O standards such as LVTTL, LVCMOS, SSTL-2, SSTL-18, HSTL-18, HSTL-15, PCI, and PCI-X to interface with other on-board devices. Single-ended I/O standards are critical when working with advanced memory devices such as double-data rate (DDR and DDR2) SDRAM and QDRII SRAM devices. The table lists the single-ended I/O standards and target performance supported in Cyclone II devices.
- From high-speed backplane applications to high-end switch boxes, low-voltage differential signaling (LVDS) is the technology of choice. LVDS is a low-voltage differential signaling standard, allowing higher noise immunity than single-ended I/O technologies. Its low-voltage swing allows for high-speed data transfers, low power consumption, and reduced electromagnetic interference (EMI).
- Cyclone II device IOEs contain a bidirectional I/O buffer and three registers for complete embedded bidirectional single data rate transfer. The IOE contains one input register, one output register, and one output enable register. You canuse the input registers for fast setup times and output registers for fast clock-to-output times. Additionally, you can use the output enable (OE) register for fast clock-to-output enable timing. The IOEs are located in I/O blocks around the periphery of the Cyclone II device. There are up to five IOEs per row I/O block and up to four IOEs per column I/O block (column I/O blocks span two columns). The row I/O blocks drive row, column (only C4 interconnects), or direct link interconnects. The column I/O blocks drive column interconnects.
- The output buffer for each Cyclone II device I/O pin has a programmable drive strength control for certain I/O standards. The LVTTL, LVCMOS, SSTL-2 class I and II, SSTL-18 class I and II, HSTL-18 class I and II, and HSTL-1.5 class I and II standards have several levels of drive strength that you can control. Using minimum settings provides signal slew rate control to reduce system noise and signal overshoot. The table shows the possible settings for the I/O standards with drive strength control.
- PCI Express is rapidly establishing itself as the successor to PCI, It provides higher performance, increased flexibility, and scalability for next-generation systems without increasing costs, all while maintaining software compatibility with existing PCI applications. Now you can easily design high volume, low-cost PCI Express ×1 solutions today with Cyclone II FPGA (EP2C15 or larger). Cyclone® II devices offer hot socketing (also known as hot plug-in, hot insertion, or hot swap) and power sequencing support without the use of any external devices. You can insert or remove a Cyclone II board in a system during system operation without causing undesirable effects to the board or to the running system bus. The hot-socketing feature lessens the board design difficulty when using Cyclone II devices on printed circuit boards (PCBs) that also contain a mixture of 3.3-, 2.5-, 1.8-, and 1.5-V devices. With the Cyclone II hot-socketing feature, you no longer need to ensure a proper power-up sequence for each device on the board.
- The I/O pins on Cyclone II devices are grouped together into I/O banks and each bank has a separate power bus. EP2C5 and EP2C8 devices have four I/O banks (see Figure 2–28), while EP2C20 to ECP2C70 devices have eight I/O banks.Each device I/O pin is associated with one I/O bank. To accommodate voltage-referenced I/O standards, each Cyclone II I/O bank has a VREF bus. Each bank in EP2C5, EP2C8, EP2C15, EP2C20, EP2C35, and EP2C50 devices supports two VREF pins and each bank of EP2C70 supports four VREF pins.
- Cyclone® II devices have up to four phase-locked loops (PLLs) that provide robust clock management and synthesis for device clock management, external system clock management, and I/O interfaces. Cyclone II PLLs are versatile and can be used as a zero delay buffer, a jitter attenuator, a low skew fan out buffer, or a frequency synthesizer. Cyclone II PLLs support four clock feedback modes: normal mode, zero delay buffer mode, no compensation mode, and source synchronous mode. Cyclone II PLLs do not have support for external feedback mode. All the supported clock feedback modes allow for multiplication and division, phase shifting, and programmable duty cycle.
- In the Active Serial configuration scheme, Cyclone II devices are configured using a serial configuration device. These configuration devices are low-cost devices with non-volatile memory that feature a simple, four-pin interface and a small form factor. These features make serial configuration devices an ideal low-cost configuration solution.
- The table shows the approximate uncompressed configuration file sizes for Cyclone II devices. To calculate the amount of storage space required for multiple device configurations, add the file size of each device together.
- Cyclone II devices include a powerful FPGA feature set optimized for low-cost applications including a wide range of density, memory, embedded multiplier, and packaging options. The low cost and optimized feature set of Cyclone II FPGAs make them ideal solutions for a wide array of automotive, consumer, communications, video processing, test and measurement, and other end-market solutions.
- Thank you for taking the time to view this presentation on Altera Cyclone II Series. If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simple call our sales hotline. For more technical information you may either visit the Altera’s site , or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.