SlideShare une entreprise Scribd logo
1  sur  31
EMEC245
Industrial Control Systems II
Advanced PLC’s and PAC’s
Indirect and Indexed Addresses (SLC500 and
LogixPro)
Includes arrays (ControlLogix)
Chapter 09
3
Valid Addressing Modes
 There are four basic modes or types of
addressing in the SLC500 series PLC’s
 Direct
 Indexed direct
 Indirect
 Indexed indirect
4
Direct Addressing
 Data is stored in the specified address.
 This mode is what we have been using for
all of our work in the course.
 Examples:
 N7:3
 T4:9.PRE
 R6:3.POS
 F8:7
 B3:6/2
 C5:8.ACC
Memory Address Data Value
N7:0 52
N7:1 128
N7:2 346
N7:3 510
N7:4 14
5
Indirect Addressing
 The address in the instruction serves as a
reference point and does not point directly
to the data location. In other words: the
instructions memory address contains the
address of a memory location.
Memory
Address
Data
Values
2210 52
2211 128
2212 345
2213 510
2214 343
Memory
Address
Data
Values
343 54
344 71
345 633
346 85
347 500
Address = 2212 Data = 633
6
Indirect Addressing
 An address can be specified as indirect by
replacing the file number, element number
or sub-element number with another word
address.
 The indirect address is always enclosed in
square brackets [ ].
 N7:[N7:0] is an example of an indirect
address.
 The word level address in the square brackets
is queried for a value. The queried value then
becomes the file, element or sub-element
portion of the indirect address.
7
Indirect Address
Examples
 N7:[N7:0]
 If a value of 43 is stored in N7:0, the indirect
address N7:[N7:0] is indirectly referencing
N7:43
 B3:[T4:0.ACC]
 If the value of 12 is stored in the accumulator
of T4:0, the indirect address B3:[T4:0.ACC] is
indirectly referencing B3:12
 F[N7:3]:[N26:12]
 If a value of 18 is stored in N7:3 and a value
of 4 is stored in N26:12, the indirect address
F[N7:3]:[N26:12] is indirectly referencing
F18:4
8
 Guidelines for specifying indirect
addresses:
 The
 file number
 word number (element + sub-element)
 bit number
can be addressed indirectly
 The substitute address must be a word-
level address.
 Enter the substitute address in square
brackets [ ].
Indirect Addressing
9
 The table shows some additional examples
of indirect addressing:
Indirect Addressing
Valid Address Variable Explanation
N7:[C5:7.ACC] Word number The word number of N7 is
being specified by the value
stored in the accumulator of
C5:7
B3:0/[R6:4.POS] Bit number The bit number of B3:0 is
being specified by the value
stored in the position word of
R6:4
N[N7:0]:[N22:1] File and word
number
The file number is stored in
N7:0 and the word number is
stored in N22:1
I:[N10:0].1/1 Slot number The slot number is stored in
N10:0
10
Indirect Addressing
When using indirect addressing, the data file
(memory location) being referenced must
exist. Data files (memory) is not
dynamically created or expanded. In other
words, the memory is not dynamically
allocated to fit the size of the data.
IMPORTANT
11
Indirect Addressing
 Indirect addressing allows for the
 creation of less complex ladder logic
 preservation of memory
 use of an array like structure
 Indirect addressing can be used for
applications such as cycling through a
recipe file in a multiple batch operation.
12
 Example application of Indirect
Addressing:
 Data collection is an application for indirect
addressing such as, keeping a record of
temperature at prescribed times and over a
given period of time.
 Using recipes in systems that require different
parameters depending upon the product being
produced.
Discuss the LogixPro Batch Process Recipe
Example
Indirect Example
13
 An indexed address is an addressing mode
for referencing a memory location that is
the original memory address plus a value
that is stored in an index register.
 The content of the index register is added
to the original address to obtain the final
memory location (offset).
 Indexed addressing is useful for accessing
elements of an array of data. The base
address stays the same, but the value of
the index register is incremented.
Indexed Addressing
14
 The table shows an example of an indexed
address:
Indexed Addressing
Memory
Address
Data
Value
N7:33 52
N7:34 578
N7:35 79
N7:36 427
N7:37 56
N7:38 4
N7:39 131
Base address = N7:22
Index or Offset = 15
Data = 56
N7:22 → (Word 22 + 15) = N7:37
15
 An address is specified as being “indexed”
by placing the “#” character in front of the
address.
 When the program encounters an address
of this form, the processor takes the
element (word) number of the address
and adds to it the value stored in the
index register.
 The index register is in the
SLC500/LogixPro Processor Status file at:
S:24
Indexed Addressing
16
 The actual address is the Base address
plus the value stored in the index register.
 Example:
 #N7:10
 Here, the element (word) number of the direct
address (the base address) is 10.
 If S:24 has a value of 25 stored in it, the value of 25
is added to the base address element number; in this
case 10.
 The address that #N7:10 with S:24 = 25 is
referencing is N7:35.
 N7:10 + S:24 or N7:10 + 25 = N7:35
Indexed Addressing
17
 When the processor resolves an Indexed
Indirect address it first resolves the
indirect portion of the address and then
adds the offset from the index register
S:24 to create the final address.
 What makes the addressing mode
powerful is that S:24 is a dynamic
address. It can be read and written to on-
the-fly.
Indexed Indirect
Addressing
18
 An address can be specified as a
combination of indirect and indexed
addressing.
 Example:
 #N7:[N10:3]
 If a value of 20 is stored in N10:3 and a value of 10
is stored in S:24, then the indexed indirect address
#N7:[N10:3] is referencing N7:30
 That is, N7:[N10:3] is indirectly referencing N7:20
and #N7:[N10:3] is indexed by 10 producing
N7:20 + 10 = N7:30
Indexed Indirect
Addressing
LogixPro does not support this mode of addressing
19
 Guidelines for specifying indexed
addresses:
 The offset value stored in S:24 can be positive
or negative.
 The offset value should not cause the base
address to cross a file boundary.
 If an instruction uses more than one indexed
address, the processor uses the same index
value on each of the indexed addresses.
 The value of the index register should be set
immediately before enabling the instruction
that uses an indexed address.
Indexed Indirect
Addressing
20
 Guidelines for specifying indexed
addresses:
 Indexed addressing does not work with
Timers, Counters or the Control File.
 Indexed addressing is invalid for any file type
that used multiple words.
 Some instructions modify the value of the
index register so that they can function
properly. The Sequencer and the Bit Shift
instructions, talked about later in this course,
is an example of instructions that use and
modify the value of S:24.
Indexed Indirect
Addressing
Monitoring Indexed
Addresses
 The value of the
indexed address
will not display
when it is being
monitored.
 The code snippet
shown assumes
that:
 S:24 = 5
 N7:3 = 123
 N7:8 = 456
When the MOV instruction is executed
the indexed address #N7:3 is evaluated
to N7:8 and the value of the indexed
address will be stored and displayed in
the direct address of N10:3. Also note in
the ADD instruction that the value stored
in the indexed address is added to the
zero of C5:0.ACC.
Arrays
ControlLogix
23
 The ControlLogix processors do not use
indexed or indirect addressing. The
ControlLogix processors use arrays.
 Arrays – An array is a tag that holds multiple
values of the same data type.
 Your textbook defines an array as: “a data
structure that allocates a contiguous block of
memory to store a specific data type as a table
of values.
ControlLogix Arrays
24
 Arrays are specified as having dimensions.
They can be:
 1-dimensional
 2-dimensional
 3-dimensional
ControlLogix Arrays
ControlLogix Arrays
ControlLogix Arrays
Tag Name Data Type
Dimension
0
Dimension
1
Dimension
2
Total # of
Elements
one_d_array DINT[7] 7 0 0 7
two_d_array DINT[4,5] 4 5 0 20
three_d_array DINT[2,3,4] 2 3 4 24
Creating an Array
Enter a tag name
Click this button
to open the
Select Data Type
Dialog box
Creating and Array
Select the data
type, then
enter the
number of
elements for
each
dimension.
Use Dim0 for a
1-dimensional
array, Dim0
and Dim1 for a
2-dimensional
array and
Dim0, Dim1
and Dim2 for a
3-dimensional
array.
Creating an Array
This Select Data
Type dialog box
shows a DINT
data type
configured as a
3-dimensional
array. Note how
the array
elements are
designated in
the Data Types:
box.
ControlLogix Arrays
   
 
396,2
396,25
5
5




esultRMOVAfter
Array
ArrayterPoinArray
terPoin
Menu Application
 This example copies 1-of-4 user
selected recipes to the batch
parameters of a batch process.
 The COP instruction shown will copy
the content of 4-words from a two-
dimensional array referenced in the
source, to a one-dimensional array in
the destination. (The COP will be
discussed in the next unit).
 The source tag is referencing a two-
dimensional array:
Recipe[RecipeNumber, 0]. Note that
the first dimension of the array is a
tag. This tag stores the value of the
recipe number selected by a user and
is used to point to 1-of-4 of the
recipes.
 If the user selects recipe number 2, the
data stored in Recipe[2,0],
Recipe[2,1], Recipe[2,2] and
Recipe[2,3] will be copied to:
BatchRecipe[0] through BatchRecipe[3]
respectively.
0
1
2
3

Contenu connexe

Similaire à 01 indirect indexed_addressing_and_arrays_sp15

Assignment on different types of addressing modes
Assignment on different types of addressing modesAssignment on different types of addressing modes
Assignment on different types of addressing modesNusratJahan263
 
Memory Reference Instructions
Memory Reference InstructionsMemory Reference Instructions
Memory Reference InstructionsRabin BK
 
Ch12- instruction sets- char & funct.pdf
Ch12- instruction sets- char & funct.pdfCh12- instruction sets- char & funct.pdf
Ch12- instruction sets- char & funct.pdfsaimawarsi
 
Design of QSD Number System Addition using Delayed Addition Technique
Design of QSD Number System Addition using Delayed Addition TechniqueDesign of QSD Number System Addition using Delayed Addition Technique
Design of QSD Number System Addition using Delayed Addition TechniqueKumar Goud
 
Design of QSD Number System Addition using Delayed Addition Technique
Design of QSD Number System Addition using Delayed Addition TechniqueDesign of QSD Number System Addition using Delayed Addition Technique
Design of QSD Number System Addition using Delayed Addition TechniqueKumar Goud
 
Data representation computer architecture
Data representation  computer architectureData representation  computer architecture
Data representation computer architecturestudy cse
 
An overview of siemens plc address mapping
An overview of siemens plc address mappingAn overview of siemens plc address mapping
An overview of siemens plc address mappingJustEngineering
 
Instruction Set Architecture: MIPS
Instruction Set Architecture: MIPSInstruction Set Architecture: MIPS
Instruction Set Architecture: MIPSPrasenjit Dey
 
Variables in Visual Basic Programming
Variables in Visual Basic ProgrammingVariables in Visual Basic Programming
Variables in Visual Basic ProgrammingKasun Ranga Wijeweera
 
C programming session 05
C programming session 05C programming session 05
C programming session 05Vivek Singh
 
Advanced computer architect lesson 3 and 4
Advanced computer architect lesson 3 and 4Advanced computer architect lesson 3 and 4
Advanced computer architect lesson 3 and 4Ismail Mukiibi
 

Similaire à 01 indirect indexed_addressing_and_arrays_sp15 (20)

Assignment on different types of addressing modes
Assignment on different types of addressing modesAssignment on different types of addressing modes
Assignment on different types of addressing modes
 
Memory Reference Instructions
Memory Reference InstructionsMemory Reference Instructions
Memory Reference Instructions
 
Ch12- instruction sets- char & funct.pdf
Ch12- instruction sets- char & funct.pdfCh12- instruction sets- char & funct.pdf
Ch12- instruction sets- char & funct.pdf
 
Design of QSD Number System Addition using Delayed Addition Technique
Design of QSD Number System Addition using Delayed Addition TechniqueDesign of QSD Number System Addition using Delayed Addition Technique
Design of QSD Number System Addition using Delayed Addition Technique
 
Design of QSD Number System Addition using Delayed Addition Technique
Design of QSD Number System Addition using Delayed Addition TechniqueDesign of QSD Number System Addition using Delayed Addition Technique
Design of QSD Number System Addition using Delayed Addition Technique
 
DIGITAL DESIGN
DIGITAL DESIGNDIGITAL DESIGN
DIGITAL DESIGN
 
Csc 2313 (lecture 3)
Csc 2313 (lecture 3)Csc 2313 (lecture 3)
Csc 2313 (lecture 3)
 
Csc 2313 (lecture 3)
Csc 2313 (lecture 3)Csc 2313 (lecture 3)
Csc 2313 (lecture 3)
 
Data representation computer architecture
Data representation  computer architectureData representation  computer architecture
Data representation computer architecture
 
An overview of siemens plc address mapping
An overview of siemens plc address mappingAn overview of siemens plc address mapping
An overview of siemens plc address mapping
 
digital-180612132737.pdf
digital-180612132737.pdfdigital-180612132737.pdf
digital-180612132737.pdf
 
Instruction Set Architecture: MIPS
Instruction Set Architecture: MIPSInstruction Set Architecture: MIPS
Instruction Set Architecture: MIPS
 
Data structures using c
Data structures using cData structures using c
Data structures using c
 
Variables in Visual Basic Programming
Variables in Visual Basic ProgrammingVariables in Visual Basic Programming
Variables in Visual Basic Programming
 
Data structures using C
Data structures using CData structures using C
Data structures using C
 
C programming session 05
C programming session 05C programming session 05
C programming session 05
 
Advanced computer architect lesson 3 and 4
Advanced computer architect lesson 3 and 4Advanced computer architect lesson 3 and 4
Advanced computer architect lesson 3 and 4
 
hashing.pdf
hashing.pdfhashing.pdf
hashing.pdf
 
Chapter1-bag2-mikroprocessor
Chapter1-bag2-mikroprocessorChapter1-bag2-mikroprocessor
Chapter1-bag2-mikroprocessor
 
Chapter7.2-mikroprocessor
Chapter7.2-mikroprocessorChapter7.2-mikroprocessor
Chapter7.2-mikroprocessor
 

Plus de John Todora

04 scaling analog_datal_sp17
04 scaling analog_datal_sp1704 scaling analog_datal_sp17
04 scaling analog_datal_sp17John Todora
 
03 analog control_sp17
03 analog control_sp1703 analog control_sp17
03 analog control_sp17John Todora
 
Comparison instructions, AB, Siemens and AB CCW
Comparison instructions, AB, Siemens and AB CCWComparison instructions, AB, Siemens and AB CCW
Comparison instructions, AB, Siemens and AB CCWJohn Todora
 
Subroutines rev01 fa16
Subroutines rev01 fa16Subroutines rev01 fa16
Subroutines rev01 fa16John Todora
 
Move mask moves_rev01_fa16
Move mask moves_rev01_fa16Move mask moves_rev01_fa16
Move mask moves_rev01_fa16John Todora
 
Math cl ccw_siemens_rev01_fa16
Math cl ccw_siemens_rev01_fa16Math cl ccw_siemens_rev01_fa16
Math cl ccw_siemens_rev01_fa16John Todora
 
ControlLogix Counters FA16
ControlLogix Counters FA16ControlLogix Counters FA16
ControlLogix Counters FA16John Todora
 
ControlLogix Timers FA16
ControlLogix Timers FA16ControlLogix Timers FA16
ControlLogix Timers FA16John Todora
 
02 chapter02 fa16
02 chapter02 fa1602 chapter02 fa16
02 chapter02 fa16John Todora
 
01 introduction to_plc-pac_rev01_fa16
01 introduction to_plc-pac_rev01_fa1601 introduction to_plc-pac_rev01_fa16
01 introduction to_plc-pac_rev01_fa16John Todora
 
07 chapter07 loop_diagrams
07 chapter07 loop_diagrams07 chapter07 loop_diagrams
07 chapter07 loop_diagramsJohn Todora
 
06 chapter06 binary_logic_systems_Rev02
06 chapter06 binary_logic_systems_Rev0206 chapter06 binary_logic_systems_Rev02
06 chapter06 binary_logic_systems_Rev02John Todora
 
04 chapter04 specification_forms
04 chapter04 specification_forms04 chapter04 specification_forms
04 chapter04 specification_formsJohn Todora
 
03 chapter03 lists_indexes_databases
03 chapter03 lists_indexes_databases03 chapter03 lists_indexes_databases
03 chapter03 lists_indexes_databasesJohn Todora
 
02 chapter02 p&ids_and_symbols_split_animations
02 chapter02 p&ids_and_symbols_split_animations02 chapter02 p&ids_and_symbols_split_animations
02 chapter02 p&ids_and_symbols_split_animationsJohn Todora
 
01 chapter01 process_flow_diagram
01 chapter01 process_flow_diagram01 chapter01 process_flow_diagram
01 chapter01 process_flow_diagramJohn Todora
 
EMEC130 P&ID Symbol Primer
EMEC130 P&ID Symbol PrimerEMEC130 P&ID Symbol Primer
EMEC130 P&ID Symbol PrimerJohn Todora
 

Plus de John Todora (20)

04 scaling analog_datal_sp17
04 scaling analog_datal_sp1704 scaling analog_datal_sp17
04 scaling analog_datal_sp17
 
03 analog control_sp17
03 analog control_sp1703 analog control_sp17
03 analog control_sp17
 
Comparison instructions, AB, Siemens and AB CCW
Comparison instructions, AB, Siemens and AB CCWComparison instructions, AB, Siemens and AB CCW
Comparison instructions, AB, Siemens and AB CCW
 
Lab02 review
Lab02 reviewLab02 review
Lab02 review
 
Subroutines rev01 fa16
Subroutines rev01 fa16Subroutines rev01 fa16
Subroutines rev01 fa16
 
Move mask moves_rev01_fa16
Move mask moves_rev01_fa16Move mask moves_rev01_fa16
Move mask moves_rev01_fa16
 
Math cl ccw_siemens_rev01_fa16
Math cl ccw_siemens_rev01_fa16Math cl ccw_siemens_rev01_fa16
Math cl ccw_siemens_rev01_fa16
 
ControlLogix Counters FA16
ControlLogix Counters FA16ControlLogix Counters FA16
ControlLogix Counters FA16
 
Lab02 lead in
Lab02 lead inLab02 lead in
Lab02 lead in
 
ControlLogix Timers FA16
ControlLogix Timers FA16ControlLogix Timers FA16
ControlLogix Timers FA16
 
02 chapter02 fa16
02 chapter02 fa1602 chapter02 fa16
02 chapter02 fa16
 
01 introduction to_plc-pac_rev01_fa16
01 introduction to_plc-pac_rev01_fa1601 introduction to_plc-pac_rev01_fa16
01 introduction to_plc-pac_rev01_fa16
 
07 chapter07 loop_diagrams
07 chapter07 loop_diagrams07 chapter07 loop_diagrams
07 chapter07 loop_diagrams
 
06 chapter06 binary_logic_systems_Rev02
06 chapter06 binary_logic_systems_Rev0206 chapter06 binary_logic_systems_Rev02
06 chapter06 binary_logic_systems_Rev02
 
04 chapter04 specification_forms
04 chapter04 specification_forms04 chapter04 specification_forms
04 chapter04 specification_forms
 
03 chapter03 lists_indexes_databases
03 chapter03 lists_indexes_databases03 chapter03 lists_indexes_databases
03 chapter03 lists_indexes_databases
 
02 chapter02 p&ids_and_symbols_split_animations
02 chapter02 p&ids_and_symbols_split_animations02 chapter02 p&ids_and_symbols_split_animations
02 chapter02 p&ids_and_symbols_split_animations
 
01 chapter01 process_flow_diagram
01 chapter01 process_flow_diagram01 chapter01 process_flow_diagram
01 chapter01 process_flow_diagram
 
00 introduction
00 introduction00 introduction
00 introduction
 
EMEC130 P&ID Symbol Primer
EMEC130 P&ID Symbol PrimerEMEC130 P&ID Symbol Primer
EMEC130 P&ID Symbol Primer
 

Dernier

Understanding Accommodations and Modifications
Understanding  Accommodations and ModificationsUnderstanding  Accommodations and Modifications
Understanding Accommodations and ModificationsMJDuyan
 
UGC NET Paper 1 Mathematical Reasoning & Aptitude.pdf
UGC NET Paper 1 Mathematical Reasoning & Aptitude.pdfUGC NET Paper 1 Mathematical Reasoning & Aptitude.pdf
UGC NET Paper 1 Mathematical Reasoning & Aptitude.pdfNirmal Dwivedi
 
Grant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy ConsultingGrant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy ConsultingTechSoup
 
SKILL OF INTRODUCING THE LESSON MICRO SKILLS.pptx
SKILL OF INTRODUCING THE LESSON MICRO SKILLS.pptxSKILL OF INTRODUCING THE LESSON MICRO SKILLS.pptx
SKILL OF INTRODUCING THE LESSON MICRO SKILLS.pptxAmanpreet Kaur
 
Spellings Wk 3 English CAPS CARES Please Practise
Spellings Wk 3 English CAPS CARES Please PractiseSpellings Wk 3 English CAPS CARES Please Practise
Spellings Wk 3 English CAPS CARES Please PractiseAnaAcapella
 
Magic bus Group work1and 2 (Team 3).pptx
Magic bus Group work1and 2 (Team 3).pptxMagic bus Group work1and 2 (Team 3).pptx
Magic bus Group work1and 2 (Team 3).pptxdhanalakshmis0310
 
Accessible Digital Futures project (20/03/2024)
Accessible Digital Futures project (20/03/2024)Accessible Digital Futures project (20/03/2024)
Accessible Digital Futures project (20/03/2024)Jisc
 
Seal of Good Local Governance (SGLG) 2024Final.pptx
Seal of Good Local Governance (SGLG) 2024Final.pptxSeal of Good Local Governance (SGLG) 2024Final.pptx
Seal of Good Local Governance (SGLG) 2024Final.pptxnegromaestrong
 
Third Battle of Panipat detailed notes.pptx
Third Battle of Panipat detailed notes.pptxThird Battle of Panipat detailed notes.pptx
Third Battle of Panipat detailed notes.pptxAmita Gupta
 
Python Notes for mca i year students osmania university.docx
Python Notes for mca i year students osmania university.docxPython Notes for mca i year students osmania university.docx
Python Notes for mca i year students osmania university.docxRamakrishna Reddy Bijjam
 
Russian Escort Service in Delhi 11k Hotel Foreigner Russian Call Girls in Delhi
Russian Escort Service in Delhi 11k Hotel Foreigner Russian Call Girls in DelhiRussian Escort Service in Delhi 11k Hotel Foreigner Russian Call Girls in Delhi
Russian Escort Service in Delhi 11k Hotel Foreigner Russian Call Girls in Delhikauryashika82
 
How to Manage Global Discount in Odoo 17 POS
How to Manage Global Discount in Odoo 17 POSHow to Manage Global Discount in Odoo 17 POS
How to Manage Global Discount in Odoo 17 POSCeline George
 
psychiatric nursing HISTORY COLLECTION .docx
psychiatric  nursing HISTORY  COLLECTION  .docxpsychiatric  nursing HISTORY  COLLECTION  .docx
psychiatric nursing HISTORY COLLECTION .docxPoojaSen20
 
ICT role in 21st century education and it's challenges.
ICT role in 21st century education and it's challenges.ICT role in 21st century education and it's challenges.
ICT role in 21st century education and it's challenges.MaryamAhmad92
 
Activity 01 - Artificial Culture (1).pdf
Activity 01 - Artificial Culture (1).pdfActivity 01 - Artificial Culture (1).pdf
Activity 01 - Artificial Culture (1).pdfciinovamais
 
1029 - Danh muc Sach Giao Khoa 10 . pdf
1029 -  Danh muc Sach Giao Khoa 10 . pdf1029 -  Danh muc Sach Giao Khoa 10 . pdf
1029 - Danh muc Sach Giao Khoa 10 . pdfQucHHunhnh
 
Key note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdfKey note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdfAdmir Softic
 
ICT Role in 21st Century Education & its Challenges.pptx
ICT Role in 21st Century Education & its Challenges.pptxICT Role in 21st Century Education & its Challenges.pptx
ICT Role in 21st Century Education & its Challenges.pptxAreebaZafar22
 

Dernier (20)

Understanding Accommodations and Modifications
Understanding  Accommodations and ModificationsUnderstanding  Accommodations and Modifications
Understanding Accommodations and Modifications
 
UGC NET Paper 1 Mathematical Reasoning & Aptitude.pdf
UGC NET Paper 1 Mathematical Reasoning & Aptitude.pdfUGC NET Paper 1 Mathematical Reasoning & Aptitude.pdf
UGC NET Paper 1 Mathematical Reasoning & Aptitude.pdf
 
Grant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy ConsultingGrant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy Consulting
 
Spatium Project Simulation student brief
Spatium Project Simulation student briefSpatium Project Simulation student brief
Spatium Project Simulation student brief
 
SKILL OF INTRODUCING THE LESSON MICRO SKILLS.pptx
SKILL OF INTRODUCING THE LESSON MICRO SKILLS.pptxSKILL OF INTRODUCING THE LESSON MICRO SKILLS.pptx
SKILL OF INTRODUCING THE LESSON MICRO SKILLS.pptx
 
Spellings Wk 3 English CAPS CARES Please Practise
Spellings Wk 3 English CAPS CARES Please PractiseSpellings Wk 3 English CAPS CARES Please Practise
Spellings Wk 3 English CAPS CARES Please Practise
 
Magic bus Group work1and 2 (Team 3).pptx
Magic bus Group work1and 2 (Team 3).pptxMagic bus Group work1and 2 (Team 3).pptx
Magic bus Group work1and 2 (Team 3).pptx
 
Accessible Digital Futures project (20/03/2024)
Accessible Digital Futures project (20/03/2024)Accessible Digital Futures project (20/03/2024)
Accessible Digital Futures project (20/03/2024)
 
Seal of Good Local Governance (SGLG) 2024Final.pptx
Seal of Good Local Governance (SGLG) 2024Final.pptxSeal of Good Local Governance (SGLG) 2024Final.pptx
Seal of Good Local Governance (SGLG) 2024Final.pptx
 
Third Battle of Panipat detailed notes.pptx
Third Battle of Panipat detailed notes.pptxThird Battle of Panipat detailed notes.pptx
Third Battle of Panipat detailed notes.pptx
 
Python Notes for mca i year students osmania university.docx
Python Notes for mca i year students osmania university.docxPython Notes for mca i year students osmania university.docx
Python Notes for mca i year students osmania university.docx
 
Russian Escort Service in Delhi 11k Hotel Foreigner Russian Call Girls in Delhi
Russian Escort Service in Delhi 11k Hotel Foreigner Russian Call Girls in DelhiRussian Escort Service in Delhi 11k Hotel Foreigner Russian Call Girls in Delhi
Russian Escort Service in Delhi 11k Hotel Foreigner Russian Call Girls in Delhi
 
How to Manage Global Discount in Odoo 17 POS
How to Manage Global Discount in Odoo 17 POSHow to Manage Global Discount in Odoo 17 POS
How to Manage Global Discount in Odoo 17 POS
 
psychiatric nursing HISTORY COLLECTION .docx
psychiatric  nursing HISTORY  COLLECTION  .docxpsychiatric  nursing HISTORY  COLLECTION  .docx
psychiatric nursing HISTORY COLLECTION .docx
 
ICT role in 21st century education and it's challenges.
ICT role in 21st century education and it's challenges.ICT role in 21st century education and it's challenges.
ICT role in 21st century education and it's challenges.
 
Asian American Pacific Islander Month DDSD 2024.pptx
Asian American Pacific Islander Month DDSD 2024.pptxAsian American Pacific Islander Month DDSD 2024.pptx
Asian American Pacific Islander Month DDSD 2024.pptx
 
Activity 01 - Artificial Culture (1).pdf
Activity 01 - Artificial Culture (1).pdfActivity 01 - Artificial Culture (1).pdf
Activity 01 - Artificial Culture (1).pdf
 
1029 - Danh muc Sach Giao Khoa 10 . pdf
1029 -  Danh muc Sach Giao Khoa 10 . pdf1029 -  Danh muc Sach Giao Khoa 10 . pdf
1029 - Danh muc Sach Giao Khoa 10 . pdf
 
Key note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdfKey note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdf
 
ICT Role in 21st Century Education & its Challenges.pptx
ICT Role in 21st Century Education & its Challenges.pptxICT Role in 21st Century Education & its Challenges.pptx
ICT Role in 21st Century Education & its Challenges.pptx
 

01 indirect indexed_addressing_and_arrays_sp15

  • 1. EMEC245 Industrial Control Systems II Advanced PLC’s and PAC’s
  • 2. Indirect and Indexed Addresses (SLC500 and LogixPro) Includes arrays (ControlLogix) Chapter 09
  • 3. 3 Valid Addressing Modes  There are four basic modes or types of addressing in the SLC500 series PLC’s  Direct  Indexed direct  Indirect  Indexed indirect
  • 4. 4 Direct Addressing  Data is stored in the specified address.  This mode is what we have been using for all of our work in the course.  Examples:  N7:3  T4:9.PRE  R6:3.POS  F8:7  B3:6/2  C5:8.ACC Memory Address Data Value N7:0 52 N7:1 128 N7:2 346 N7:3 510 N7:4 14
  • 5. 5 Indirect Addressing  The address in the instruction serves as a reference point and does not point directly to the data location. In other words: the instructions memory address contains the address of a memory location. Memory Address Data Values 2210 52 2211 128 2212 345 2213 510 2214 343 Memory Address Data Values 343 54 344 71 345 633 346 85 347 500 Address = 2212 Data = 633
  • 6. 6 Indirect Addressing  An address can be specified as indirect by replacing the file number, element number or sub-element number with another word address.  The indirect address is always enclosed in square brackets [ ].  N7:[N7:0] is an example of an indirect address.  The word level address in the square brackets is queried for a value. The queried value then becomes the file, element or sub-element portion of the indirect address.
  • 7. 7 Indirect Address Examples  N7:[N7:0]  If a value of 43 is stored in N7:0, the indirect address N7:[N7:0] is indirectly referencing N7:43  B3:[T4:0.ACC]  If the value of 12 is stored in the accumulator of T4:0, the indirect address B3:[T4:0.ACC] is indirectly referencing B3:12  F[N7:3]:[N26:12]  If a value of 18 is stored in N7:3 and a value of 4 is stored in N26:12, the indirect address F[N7:3]:[N26:12] is indirectly referencing F18:4
  • 8. 8  Guidelines for specifying indirect addresses:  The  file number  word number (element + sub-element)  bit number can be addressed indirectly  The substitute address must be a word- level address.  Enter the substitute address in square brackets [ ]. Indirect Addressing
  • 9. 9  The table shows some additional examples of indirect addressing: Indirect Addressing Valid Address Variable Explanation N7:[C5:7.ACC] Word number The word number of N7 is being specified by the value stored in the accumulator of C5:7 B3:0/[R6:4.POS] Bit number The bit number of B3:0 is being specified by the value stored in the position word of R6:4 N[N7:0]:[N22:1] File and word number The file number is stored in N7:0 and the word number is stored in N22:1 I:[N10:0].1/1 Slot number The slot number is stored in N10:0
  • 10. 10 Indirect Addressing When using indirect addressing, the data file (memory location) being referenced must exist. Data files (memory) is not dynamically created or expanded. In other words, the memory is not dynamically allocated to fit the size of the data. IMPORTANT
  • 11. 11 Indirect Addressing  Indirect addressing allows for the  creation of less complex ladder logic  preservation of memory  use of an array like structure  Indirect addressing can be used for applications such as cycling through a recipe file in a multiple batch operation.
  • 12. 12  Example application of Indirect Addressing:  Data collection is an application for indirect addressing such as, keeping a record of temperature at prescribed times and over a given period of time.  Using recipes in systems that require different parameters depending upon the product being produced. Discuss the LogixPro Batch Process Recipe Example Indirect Example
  • 13. 13  An indexed address is an addressing mode for referencing a memory location that is the original memory address plus a value that is stored in an index register.  The content of the index register is added to the original address to obtain the final memory location (offset).  Indexed addressing is useful for accessing elements of an array of data. The base address stays the same, but the value of the index register is incremented. Indexed Addressing
  • 14. 14  The table shows an example of an indexed address: Indexed Addressing Memory Address Data Value N7:33 52 N7:34 578 N7:35 79 N7:36 427 N7:37 56 N7:38 4 N7:39 131 Base address = N7:22 Index or Offset = 15 Data = 56 N7:22 → (Word 22 + 15) = N7:37
  • 15. 15  An address is specified as being “indexed” by placing the “#” character in front of the address.  When the program encounters an address of this form, the processor takes the element (word) number of the address and adds to it the value stored in the index register.  The index register is in the SLC500/LogixPro Processor Status file at: S:24 Indexed Addressing
  • 16. 16  The actual address is the Base address plus the value stored in the index register.  Example:  #N7:10  Here, the element (word) number of the direct address (the base address) is 10.  If S:24 has a value of 25 stored in it, the value of 25 is added to the base address element number; in this case 10.  The address that #N7:10 with S:24 = 25 is referencing is N7:35.  N7:10 + S:24 or N7:10 + 25 = N7:35 Indexed Addressing
  • 17. 17  When the processor resolves an Indexed Indirect address it first resolves the indirect portion of the address and then adds the offset from the index register S:24 to create the final address.  What makes the addressing mode powerful is that S:24 is a dynamic address. It can be read and written to on- the-fly. Indexed Indirect Addressing
  • 18. 18  An address can be specified as a combination of indirect and indexed addressing.  Example:  #N7:[N10:3]  If a value of 20 is stored in N10:3 and a value of 10 is stored in S:24, then the indexed indirect address #N7:[N10:3] is referencing N7:30  That is, N7:[N10:3] is indirectly referencing N7:20 and #N7:[N10:3] is indexed by 10 producing N7:20 + 10 = N7:30 Indexed Indirect Addressing LogixPro does not support this mode of addressing
  • 19. 19  Guidelines for specifying indexed addresses:  The offset value stored in S:24 can be positive or negative.  The offset value should not cause the base address to cross a file boundary.  If an instruction uses more than one indexed address, the processor uses the same index value on each of the indexed addresses.  The value of the index register should be set immediately before enabling the instruction that uses an indexed address. Indexed Indirect Addressing
  • 20. 20  Guidelines for specifying indexed addresses:  Indexed addressing does not work with Timers, Counters or the Control File.  Indexed addressing is invalid for any file type that used multiple words.  Some instructions modify the value of the index register so that they can function properly. The Sequencer and the Bit Shift instructions, talked about later in this course, is an example of instructions that use and modify the value of S:24. Indexed Indirect Addressing
  • 21. Monitoring Indexed Addresses  The value of the indexed address will not display when it is being monitored.  The code snippet shown assumes that:  S:24 = 5  N7:3 = 123  N7:8 = 456 When the MOV instruction is executed the indexed address #N7:3 is evaluated to N7:8 and the value of the indexed address will be stored and displayed in the direct address of N10:3. Also note in the ADD instruction that the value stored in the indexed address is added to the zero of C5:0.ACC.
  • 23. 23  The ControlLogix processors do not use indexed or indirect addressing. The ControlLogix processors use arrays.  Arrays – An array is a tag that holds multiple values of the same data type.  Your textbook defines an array as: “a data structure that allocates a contiguous block of memory to store a specific data type as a table of values. ControlLogix Arrays
  • 24. 24  Arrays are specified as having dimensions. They can be:  1-dimensional  2-dimensional  3-dimensional ControlLogix Arrays
  • 26. ControlLogix Arrays Tag Name Data Type Dimension 0 Dimension 1 Dimension 2 Total # of Elements one_d_array DINT[7] 7 0 0 7 two_d_array DINT[4,5] 4 5 0 20 three_d_array DINT[2,3,4] 2 3 4 24
  • 27. Creating an Array Enter a tag name Click this button to open the Select Data Type Dialog box
  • 28. Creating and Array Select the data type, then enter the number of elements for each dimension. Use Dim0 for a 1-dimensional array, Dim0 and Dim1 for a 2-dimensional array and Dim0, Dim1 and Dim2 for a 3-dimensional array.
  • 29. Creating an Array This Select Data Type dialog box shows a DINT data type configured as a 3-dimensional array. Note how the array elements are designated in the Data Types: box.
  • 30. ControlLogix Arrays       396,2 396,25 5 5     esultRMOVAfter Array ArrayterPoinArray terPoin
  • 31. Menu Application  This example copies 1-of-4 user selected recipes to the batch parameters of a batch process.  The COP instruction shown will copy the content of 4-words from a two- dimensional array referenced in the source, to a one-dimensional array in the destination. (The COP will be discussed in the next unit).  The source tag is referencing a two- dimensional array: Recipe[RecipeNumber, 0]. Note that the first dimension of the array is a tag. This tag stores the value of the recipe number selected by a user and is used to point to 1-of-4 of the recipes.  If the user selects recipe number 2, the data stored in Recipe[2,0], Recipe[2,1], Recipe[2,2] and Recipe[2,3] will be copied to: BatchRecipe[0] through BatchRecipe[3] respectively. 0 1 2 3