5. Processor registers Adder-Subtractor Integer multiply Logic unit Shift Unit Incrementer Floating-point multiply Floating-point add-subtract Floating-point divide To memory Processor with multiple functional units operating in parallel
12. CU PU1 PU2 PUn Shared Memory MM1 MM2 MMn IS DS1 DS2 DSn
13.
14. CU1 CU2 CUn PU1 PU2 PUn MM1 MM2 MMm IS1 IS2 ISn IS1 IS2 ISn DS SM DS
15.
16. CU1 CU2 CUn PU1 PU2 PUn MM1 MM2 SM MMm DS1 DS2 DSn IS1 IS2 ISn IS1 IS2 ISn IS1 IS2 ISn
17.
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25. I1 I2 I3 I1 I2 I3 I1 I2 I3 I1 I2 I3 I4 EX OF ID IF a) Pipelined stages O/P I1 I2 I3 I4 I5 I1 I2 I3 I4 I5 I1 I2 I3 I4 I5 I1 I2 I3 I4 I5 EX OF ID IF 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 10 11 12 13 O/P O/P O/P b) NonPipelined stages
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31. R R Compare Exponents By subtraction R Choose exponent R R Align Mantissas Normalize result R Add or Subtract mantissas R Adjust exponent R Seg 1: Seg 2: Seg 3: Seg 4: Difference Exponents Mantissas a b A B
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36. Fetch instruction from memory Decode instruction & calculate EA Branch? Fetch Operand from memory Execute instruction Interrupt? Empty pipe Update PC Interrupt Handling Yes Yes No No Seg 1: Seg 2: Seg 3: Seg 4: Four segment CPU pipeline
37. Timing of instruction pipeline INSTRUCTION BRANCH Steps 1 2 3 4 5 6 7 8 9 10 11 12 13 1 FI DA FO EX 2 FI DA FO EX 3 FI DA FO EX 4 FI - - FI DA FO EX 5 - - - FI DA FO EX 6 FI DA FO EX 7 FI DA FO EX
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53. Memory Array Memory Array Memory Array Memory Array AR AR AR AR DR DR DR DR Address Bus Data Bus
69. CPU 1 CPU 2 CPU 3 MM 1 MM 2 MM 3 Crossbar Switch
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80. CISC versus RISC Multiple register sets Single register set Fixed format instructions variable format instructions Spends more transistors on memory registers Transistors used for storing complex instructions Low cycles per second, large code sizes Small code sizes, high cycles per second Register to register: "LOAD" and "STORE" are independent instructions Memory-to-memory: "LOAD" and "STORE" incorporated in instructions Single-clock, reduced instruction only Includes multi-clock complex instructions Emphasis on software Emphasis on hardware RISC CISC
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85. Pipeline timing with delayed load Pipeline timing with data conflict E A I 4. Store R3 E A I 3. Add R1+R2 E A I 2; LOAD R2 E A I 1; LOAD R1 6 5 4 3 2 1 Clock Cycles A E 6 E I 5. Store R3 A I 4. Add R1+R2 E A I 3. No-operation E A I 2; LOAD R2 E A I 1; LOAD R1 7 5 4 3 2 1 Clock Cycles
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