CAOS @ ICCD2017
•Télécharger en tant que PPTX, PDF•
0 j'aime•171 vues
"The role of CAD frameworks in heterogeneous FPGA-based cloud systems" talk @ ICCD2017
Recommandé
Recommandé
Contenu connexe
Similaire à CAOS @ ICCD2017
Similaire à CAOS @ ICCD2017 (20)
Plus de NECST Lab @ Politecnico di Milano
Plus de NECST Lab @ Politecnico di Milano (20)
Dernier
Dernier (20)
CAOS @ ICCD2017
- 1. 1EXTRA Consortium Proprietary ICCD 7 November 2017 L. Di Tucci, M. Rabozzi, L. Stornaiuolo and M. D. Santambrogio https://www.extrahpc.eu/
- 4. ! Usability
- 6. Modularity
- 7. 7
- 8. The proposed CAOS framework ____ __ ____ ____ __ ___ ____ ____ Application (C, C++ OPENCL) WebUI CAOSFlowManager Frontend IR generation – profiling – templates applicability check – HW/SW partitioning Functions Optimization HW resource estimation – static code analysis – performance estimation – code optimization / DSE Backend Runtime generation – function synthesis – floorplanning – bitstream generation IR gen. profiling … HW est. DSE … Floorpl. Bit. gen. … … … <system> … </system> Profiling Datasets System Description 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 10 1 0 10 1 0 1 10 1 0 10 1 1 01 0 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 System runtime FPGAs bitstreams
- 9. The proposed CAOS framework Architectural Templates ( ) OpenCL Streaming … ( ) … Computa8on Model Technology SST ____ __ ____ ____ __ ___ ____ ____ Application (C, C++ OPENCL) WebUI CAOSFlowManager Frontend IR generation – profiling – templates applicability check – HW/SW partitioning Functions Optimization HW resource estimation – static code analysis – performance estimation – code optimization / DSE Backend Runtime generation – function synthesis – floorplanning – bitstream generation IR gen. profiling … HW est. DSE … Floorpl. Bit. gen. … … … <system> … </system> Profiling Datasets System Description 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 10 1 0 10 1 0 1 10 1 0 10 1 1 01 0 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 System runtime FPGAs bitstreams
- 10. CAOS Frontend ____ __ ____ ____ __ ___ ____ ____ Application (C, C++ OPENCL) WebUI CAOSFlowManager Frontend IR generation – profiling – templates applicability check – HW/SW partitioning Functions Optimization HW resource estimation – static code analysis – performance estimation – code optimization / DSE Backend Runtime generation – function synthesis – floorplanning – bitstream generation IR gen. profiling … HW est. DSE … Floorpl. Bit. gen. … … … <system> … </system> Profiling Datasets System Description 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 10 1 0 10 1 0 1 10 1 0 10 1 1 01 0 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 System runtime FPGAs bitstreams
- 11. CAOS Functions Optimization ____ __ ____ ____ __ ___ ____ ____ Application (C, C++ OPENCL) WebUI CAOSFlowManager Frontend IR generation – profiling – templates applicability check – HW/SW partitioning Functions Optimization HW resource estimation – static code analysis – performance estimation – code optimization / DSE Backend Runtime generation – function synthesis – floorplanning – bitstream generation IR gen. profiling … HW est. DSE … Floorpl. Bit. gen. … … … <system> … </system> Profiling Datasets System Description 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 10 1 0 10 1 0 1 10 1 0 10 1 1 01 0 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 System runtime FPGAs bitstreams
- 12. CAOS Backend ____ __ ____ ____ __ ___ ____ ____ Application (C, C++ OPENCL) WebUI CAOSFlowManager Frontend IR generation – profiling – templates applicability check – HW/SW partitioning Functions Optimization HW resource estimation – static code analysis – performance estimation – code optimization / DSE Backend Runtime generation – function synthesis – floorplanning – bitstream generation IR gen. profiling … HW est. DSE … Floorpl. Bit. gen. … … … <system> … </system> Profiling Datasets System Description 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 10 1 0 10 1 0 1 10 1 0 10 1 1 01 0 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 System runtime FPGAs bitstreams
- 13. CAOS Backend ____ __ ____ ____ __ ___ ____ ____ Application (C, C++ OPENCL) WebUI CAOSFlowManager Frontend IR generation – profiling – templates applicability check – HW/SW partitioning Functions Optimization HW resource estimation – static code analysis – performance estimation – code optimization / DSE Backend Runtime generation – function synthesis – floorplanning – bitstream generation IR gen. profiling … HW est. DSE … Floorpl. Bit. gen. … … … <system> … </system> Profiling Datasets System Description 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 10 1 0 10 1 0 1 10 1 0 10 1 1 01 0 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 1 01 0 1 01 0 1 1 01 0 1 01 1 0 10 System runtime FPGAs bitstreams SST MaxCompiler Output Genera- on
- 14. CAOS: Maxeler integration • Maxeler template supported in CAOS – Template applicability check for Maxeler dataflow – Semi automatic translation from C code (with C2MaxJ) – Backend support for MaxCompiler toolchain • WIP: – Multi-FPGA support for MaxJ Kernel and Manager code – Function optimization of MaxJ code • Loop tilinh – HW resource estimation MaxCompiler</> </>
- 15. CAOS: OpenCL and SDAccel • CAOS Frontend supports OpenCL code: – Intermediate representation support – Template applicability check for SDA – Code profiling through LTPV (OpenCL profiler) – Function optimization: • Static code analysis and HW resource estimation within SDA – Backend support for SDAccell </> </>
- 16. CAOS Backend for SDAccel SDAccel generates & provides: - XCLBIN containing the bitstream - OpenCL Runtime to manage kernel execution CAOS Integrates SDAccel: - Identifying I/O Variables - Generating a specific OpenCL Host code for the application
- 17. 7 November 2017 your name / affiliation here 17
- 18. 18EXTRA Consortium Proprietary https://www.extrahpc.eu/
Notes de l'éditeur
- The framework has been designed in order to ensure usability, so that users with low-expertise on FPGA are able to use it, interactivity during the design phases to guide the user through the optimization process, modularity, so that users can upload their custom modules.
- The framework has been designed in order to ensure usability, so that users with low-expertise on FPGA are able to use it, interactivity during the design phases to guide the user through the optimization process, modularity, so that users can upload their custom modules.
- The framework has been designed in order to ensure usability, so that users with low-expertise on FPGA are able to use it, interactivity during the design phases to guide the user through the optimization process, modularity, so that users can upload their custom modules.
- The framework has been designed in order to ensure usability, so that users with low-expertise on FPGA are able to use it, interactivity during the design phases to guide the user through the optimization process, modularity, so that users can upload their custom modules.
- The framework has been designed in order to ensure usability, so that users with low-expertise on FPGA are able to use it, interactivity during the design phases to guide the user through the optimization process, modularity, so that users can upload their custom modules.
- The framework has been designed in order to ensure usability, so that users with low-expertise on FPGA are able to use it, interactivity during the design phases to guide the user through the optimization process, modularity, so that users can upload their custom modules.
- The framework has been designed in order to ensure usability, so that users with low-expertise on FPGA are able to use it, interactivity during the design phases to guide the user through the optimization process, modularity, so that users can upload their custom modules.