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VLSI – IEEE PROJECTS - 2014 LIST
S.No Project Title
IEEE -2014
1. Multiplication Acceleration Through Quarter Precision Wallace Tree Multiplier.
2. High Speed Vedic Multiplier Designs.
3. Power and Area-Efficient Approximate Wallace Tree Multiplier for Error-Resilient
Systems.
4. Design and Implementation of a High Speed Serial Peripheral Interface.
5. A Decimal / Binary Multi-operand Adder using a Fast Binary to Decimal Converter.
6. Implementation of Floating Point MAC Using Residue Number System.
7. Implementation of FIR Filter using a Novel Modulo Adder for 2n-2k-1 Residue Number
System.
8. Quaternary Arithmetic Logic Unit on a Programmable Logic Device.
9. Implementation of High Speed Low Power Combinational and Sequential Circuits using
Reversible logic.
10. Area–Delay–Power Efficient Carry-Select Adder
11. Scaled Radix-2/8 Algorithm for Efficient Computation of Length- DFTs
12. Efficient Integer DCT Architectures for HEVC
IEEE -2013
13. RTL Design and VLSI Implementation of an efficient Convolutional Encoder and
Adaptive Viterbi Decoder
14. VLSI implementation of Fast Addition using Quaternary Signed Digit Number System
15. An Efficient High Speed Wallace Tree Multiplier
16. Low-Power Design of Reed-Solomon Encoders

2. 17. An Efficient SQRT Architecture of Carry Select Adder Design by Common Boolean
Logic.
18. Enhanced Area Efficient Architecture for 128 bit Modified CSLA
19. Area Efficient Carry Select Adder using Binary Excess Code
20. Low Power Analysis of MAC using Modified Booth Algorithm
21. Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA
22. Design and Implementation of a BIST Embedded High Speed RS-422 Utilized UART
over FPGA
23. A Novel Modulo Adder for Residue Number System
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