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THE 8051
MICROCONTROLLER
8051 BASIC COMPONENT
 4K bytes internal ROM
 128 bytes internal RAM
 Four 8-bit I/O ports (P0 - P3).
 Two 16-bit timers/counters
 One serial interface
RAM
I/O
Port
Timer
Serial
COM
Port
Microcontroller
CPU
A single chip
ROM
BLOCK DIAGRAM
CPU
Interrupt
Control
OSC Bus
Control
4k
ROM
Timer 1
Timer 2
Serial
128 bytes
RAM
4 I/O Ports
TXD RXD
External Interrupts
P0 P2 P1 P3
Addr/Data
OTHER 8051 FEATURS
 only 1 On chip oscillator (external crystal)
 6 interrupt sources (2 external , 3 internal, Reset)
 64K external code (program) memory(only read)PSEN
 64K external data memory(can be read and write) by
RD,WR
 Code memory is selectable by EA (internal or external)
 We may have External memory as data and code
COMPARISON OF THE 8051 FAMILY
MEMBERS
89XX ROM RAM Timer Int
Source
IO pin Other
8951 4k 128 2 6 32 -
8952 8k 256 3 8 32 -
8953 12k 256 3 9 32 WD
8955 20k 256 3 8 32 WD
898252 8k 256 3 9 32 ISP
891051 1k 64 1 3 16 AC
892051 2k 128 2 6 16 AC
WD: Watch Dog Timer
AC: Analog Comparator
ISP: In System Programable
8051 Internal Block Diagram
MACHINE CYCLE
 Find the machine cycle for
 (a) XTAL = 11.0592 MHz
 (b) XTAL = 16 MHz.
 Solution:
 (a) 11.0592 MHz / 12 = 921.6 kHz;
 machine cycle = 1 / 921.6 kHz = 1.085 s
 (b) 16 MHz / 12 = 1.333 MHz;
 machine cycle = 1 / 1.333 MHz = 0.75 s
ADDRESS MULTIPLEXING
FOR EXTERNAL MEMORY
Figure 2-8
Accessing
external
code
memory
ACCESSING EXTERNAL
DATA MEMORY
Figure
2-11
Interface
to 1K
RAM
Timing for MOVX instruction
ON-CHIP MEMORY
INTERNAL RAM
REGISTERS
07
06
05
04
03
02
01
00
R7
R6
R5
R4
R3
R2
R1
R0
0F
08
17
10
1F
18
Bank 3
Bank 2
Bank 1
Bank 0
Four Register Banks
Each bank has R0-R7
Selectable by psw.2,3
BIT ADDRESSABLE RAM
Figure 2-6
Summary
of the 8051
on-chip
data
memory
(RAM)
SFRS THAT ARE BIT
ADDRESSABLE
SFRs with addresses
ending in 0 or 8 are
bit-addressable.
(80, 88, 90, 98, etc)
Notice that all 4 parallel
I/O ports are bit
addressable.

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