Consider the circuit in Figure 2. Suppose the maximum and minimum delay of the three pipeline stages are tauA(max) = 5ns and tauA(min)= 4ns,tauB(max)3ns and tauB(min) =1ns and tauC(max) = 3ns and tauC(min) = 200ps, respectively. Determine deltaA, deltaB, and deltaC to maximize the clock frequency if (a) the circuit has positive clock skew, and (b) the circuit has negative clock skew. Solution Clock Frequency = 1/delay To maximize the clock frequency delay will be minimum delA = 4ns delB = 1ns delC = 200ps.