Clock Tree Networks are Pillars and Columns of a Chip. With these series of lectures, we have explored on-site concepts applied in VLSI industry. It is a One-Stop-Shop to understand industrial VLSI circuits. The videos will develop an analytical approach to tackle technical challenges while building Clock Tree. https://www.udemy.com/vlsi-academy-clock-tree-synthesis/

1. Clock Tree Synthesis (CTS)
• CTS Quality Checks (Skew, Power, Latency, etc.)
• H-Tree
• Quality Check of H-Tree
• Clock Tree Buffering
• Buffered H-Tree
• H-Tree with uneven spread of Flops
• Advanced H-Tree for Million Flops
• Power Aware CTS (clock gating)
• Static Timing Analysis with Clock Tree
https://www.udemy.com/vlsi-academy-clock-tree-synthesis/ 1

2. CTS Quality Check
Check-List
1) SKEW
2) PULSE WIDTH
3) DUTY CYCLE
4) LATENCY
5) CLOCK TREE POWER
6) SIGNAL INTEGRITY AND CROSSTALK
https://www.udemy.com/vlsi-academy-clock-tree-synthesis/ 2

3. H-Tree
CLK
CHIP
Check-List
1) SKEW
2) PULSE WIDTH
3) DUTY CYCLE
4) LATENCY
5) CLOCK TREE POWER
6) SIGNAL INTEGRITY AND CROSSTALK
https://www.udemy.com/vlsi-academy-clock-tree-synthesis/ 3

4. Clock Tree Buffering
‘L’CL
‘L/4’
‘L/4’
‘L/4’
‘L/4’
A
How about creating a buffer tree at node ‘A’
B
C
C1
C2
C3
C4
Cbuf1
Cbuf2
Let us assume Cbuf1 = Cbuf2 = 30fF
Let us assume C1 = C2 = C3 = C4 = 25fF
Therefore, total Cap at node ‘A’ => 60fF
Therefore, total Cap at node ‘B’ => 50fF
Therefore, total Cap at node ‘C’ => 50fF
Level 1
Level 2 Observations
• 2 levels of buffering
• At every level, each
node driving same
load
• Identical buffer at
same level
https://www.udemy.com/vlsi-academy-clock-tree-synthesis/ 4

5. Buffered H-Tree
CLK
CHIP
Observations
• Levels of buffering
• At every level, each
node driving same
load
• Identical buffer at
same level
https://www.udemy.com/vlsi-academy-clock-tree-synthesis/ 5

6. • H-Tree with uneven spread of Flops
CLK
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
Check-List
1) SKEW
2) PULSE WIDTH
3) DUTY CYCLE
4) LATENCY
5) CLOCK TREE POWER
6) SIGNAL INTEGRITY AND CROSSTALK
L1 = 5 Buffer Delays + 6 Wire Delays
PTOTAL = 16 ([CV2 + V.I.t]S0->1 + VILEAK)
L1
https://www.udemy.com/vlsi-academy-clock-tree-synthesis/ 6

7. Advanced H-Tree for Million Flops
C
C
C
C
https://www.udemy.com/vlsi-academy-clock-tree-synthesis/ 7

8. C
C
Power Aware CTS
EN1
Switching and Short Circuit
Power Saved
Only Leakage power
consumed
https://www.udemy.com/vlsi-academy-clock-tree-synthesis/ 8

9. Timing Analysis (with real Clocks)
QD QD
CLK
Launch Flop Capture Flop
ϴ
Specifications:
Clock Frequency (F) = 1GHz
Clock Period (T)= 1/F
= 1/1GHz
= 1ns
0 T
0 T
Setup Analysis - Single Clock
t
With, T = 1ns,
Assume S = 10ps
= 0.01ns
Uncertainty = 90ps
= 0.09ns
1
2
3 4
Δ1 Δ2
Data Required Time
- Data Arrival Time
---------------------------
SLACK (should be +ve or ‘0’)
SSU
x
(ϴ+Δ1) < (T+ Δ2 + 3x) - S - SU
Data Required TimeData Arrival Time
x
x
https://www.udemy.com/vlsi-academy-clock-tree-synthesis/ 9

10. Timing Analysis (with real Clocks)
QD QD
CLK
Launch Flop Capture Flop
ϴ
Specifications:
Clock Frequency (F) = 1GHz
Clock Period (T)= 1/F
= 1/1GHz
= 1ns
Hold Analysis - Single Clock
0 T
0 t
ϴ+Δ1 > H+Δ2 +3x +HUH
1
2
3 4
With, T = 1ns,
Assume H = 10ps
= 0.01ns
Uncertainty = 50ps
= 0.05ns
Data Required TimeData Arrival TimeData Arrival Time
- Data Required Time
---------------------------
SLACK(should be +ve or ‘0’)
x
x
x
https://www.udemy.com/vlsi-academy-clock-tree-synthesis/ 10

11. https://www.udemy.com/vlsi-academy-clock-tree-synthesis/ 11

12. https://www.udemy.com/vlsi-academy-clock-tree-synthesis/
https://www.udemy.com/vlsi-academy-clock-tree-synthesis/ 12