Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers

1. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers Eng. MshariAlabdulkarim

3. Baseline Design.

4. Reducing Conflict Misses.

7. VAX 11/780 is a complex instruction set computer (CISC) machine.

8. VAX-11/780 was the first model of VAX machines, and it has been introduced on October 25, 1977.

10. Direct-Mapped Cache Performance Baseline Design (1):

12. The first & second level caches are assumed to be direct-mapped ⟹ “fastest effective access time”.

13. The data cache can be either write-through or write-back. How to obtain? 1 2 3 Very fast on-chip clock Issuing many inst. per cycle Using higher speed technology for the processor chip

15. There are two separate first-level caches: instruction and data caches.

16. The size of the first-level caches is 4KB (with 16B lines).

17. The size of the second-level is 1MB (with 128B lines).

19. Direct-Mapped Cache Performance Baseline Design (5): Baseline system first-level cache miss rates

20. Direct-Mapped Cache Performance Baseline Design (6): Performance lost in memory hierarchy Baseline design performance Net performance of the system

22. Compulsory misses: are misses required in any cache organization because they are the first references to an instruction or piece of data.

23. Capacity misses: occur when the cache size is not sufficient to hold data between references.

26. Miss cache: is a small fully-associative cache containing on the order of two to five cache lines of data.

29. Each time the upper cache is probed, the miss cache is probed as well.

33. Direct-Mapped Cache Performance Reducing Conflict Misses (10): Conflict misses removed by victim caching

34. Direct-Mapped Cache Performance Reducing Conflict Misses (11): Victim cache performance with varying direct-mapped data cache size

36. Capacity misses occur when the cache size is not sufficient to hold data between references.

38. Direct-Mapped Cache Performance Reducing Capacity and Compulsory Misses (3): Limited time for prefetch

39. Direct-Mapped Cache Performance Reducing Capacity and Compulsory Misses (4): Stream Buffers: Goal: start the prefetch before a tag transition can take place.

41. As each prefetch request is sent out, the tag for the address is entered into the stream buffer, and the available bit is set to false.

42. When the prefetch data returns it is placed in the entry with its tag and the available bit is set to true.

43. If a reference misses in the cache but hits in the buffer the cache can be reloaded in a single cycle from the stream buffer.

47. Direct-Mapped Cache Performance Reducing Capacity and Compulsory Misses (8): Four-way stream buffer performance

48. Direct-Mapped Cache Performance Reducing Capacity and Compulsory Misses (9): Stream buffer performance vs. cache size

49. Direct-Mapped Cache Performance Reducing Capacity and Compulsory Misses (10): Stream buffer performance vs. line size

50. Direct-Mapped Cache Performance System performance with victim cache and stream buffers

51. Direct-Mapped Cache Performance Reference: N. P Jouppi, “Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers,” in Computer Architecture, 1990. Proceedings., 17th Annual International Symposium on, 2002, 364–373.

52. Direct-Mapped Cache Performance Thank you for your attention