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VGA VHDL RTL design tutorial

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Nabil Chouba
Nabil Chouba

VGA VHDL RTL design tutorial

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VGA - Display Example 1: Diagonal line display Example 2: Cam To VGA Example 3: Keyboard to VGA by Nabil CHOUBA
Cathode Ray Tubes
Sync signal horizontal sync vertical sync
DB15 connector DAC ! RGB Color 000 black 001 blue 010 green 011 cyan 100 red 101 magenta 110 yellow 111 white
VGA video signal generation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
VGA feature ,[object Object],[object Object],[object Object]
horizontal sync 640 660 756 800 Front porch TFP Back porch TBP Pulse width TPW
vertical sync 480 494 495 525 Front porch TFP Back porch TBP Pulse width TPW
VGA sync generation -- horiz_sync ------------------------------------__________-------- -- h_count 0 640 659 755 799 process (h_count_reg) begin h_count_next <=h_count_reg ; if (h_count_reg = 799) then h_count_next <= (others=>'0') ; else h_count_next <= h_count_reg + 1; end if; end process ; --generate horizontal sync signal using h_count horiz_sync <= '0' when (h_count_reg <= 755) and (h_count_reg >= 659) else '1'; ,[object Object],[object Object]
VGA sync generation -- vert_sync -----------------------------------------------_______------------ -- v_count 0 480 493 494 524 process (v_count_reg,h_count_reg) begin v_count_next <= v_count_reg; if (v_count_reg >= 524) and (h_count_reg >= 699) then v_count_next <= (others=>'0') ; elsif (h_count_reg = 699) then v_count_next <= v_count_reg + 1; end if; end process; -- generate vertical sync signal using v_count vert_sync <= '0' when (v_count_reg <= 494) and (v_count_reg >= 493) else '1'; ,[object Object],[object Object]
VGA sync generation -- generate video on screen signals for pixel data video_on_h <= '1' when (h_count_reg <= 639) else '0'; video_on_v <= '1' when (v_count_reg <= 479) else '0'; -- video_on is high only when rgb data is displayed video_on <= video_on_h and video_on_v; cloked_process : process( clk_25mhz, rst ) begin if( rst='1' ) then h_count_reg <= (others=>'0') ; v_count_reg <= (others=>'0') ; elsif( clk_25mhz'event and clk_25mhz='1' ) then h_count_reg <= h_count_next; v_count_reg <= v_count_next; end if; end process ;
Elementary graphics card sync generation counters pixel RAM or / and pixel generator row col 25MHz clock R G B hsync vsync BinData to display or / and OpenGL instruction Vedio_on
exp1 : Line On Diagonal ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
VGA sync generation I/O Pin Assignments ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
vga_sync CanAdressGen Vsyn Hsyc pixel_data cam_Y Pixel_adrs green blue red vert_sync horiz_sync clk_25mhz clk_cam VGA Screen OmniVision OV6620 CMOS image sensor. exp2 : Cam To VGA cam_Y Size :352x288 Pclk2 :4.4M Size :640x480 Pclk1 :25M ram_dual Dual Port RAM D1 Q1 adrs1 adrs2 we1 Port A Port B clk2 clk1
Dual Port RAM coding style entity ram_dual is generic( d_width : integer ; addr_width : integer ; mem_depth : integer ); port ( o2 : out STD_LOGIC_VECTOR(d_width - 1 downto 0); we1 : in STD_LOGIC; clk1 : in STD_LOGIC; d1 : in STD_LOGIC_VECTOR(d_width - 1 downto 0); addr1 : in unsigned(addr_width - 1 downto 0); clk2 : in STD_LOGIC; addr2 : in unsigned(addr_width - 1 downto 0) ); end ram_dual; architecture RAM_dual_arch of ram_dual is type mem_type is array (mem_depth - 1 downto 0) of STD_LOGIC_VECTOR (d_width - 1 downto 0); signal mem : mem_type; ram_dual Dual Port RAM D1 Q1 adrs1 adrs2 we1 Port A Port B clk2 clk1
Dual Port RAM coding style begin write_port : process ( clk1 ) begin if (clk1'event and clk1 = '1') then if ( we1 = '1') then mem(conv_integer(addr1)) <= d1; end if; end if; end process write_port ; read_port : process ( clk2 ) begin if (clk2'event and clk2 = '1') then o2 <= mem(conv_integer(addr2)) ; end if; end process read_port ; end RAM_dual_arch; ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],ram_dual Dual Port RAM D1 Q1 adrs1 adrs2 we1 Port A Port B clk2 clk1
Cam : OmniVision OV6620 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Vsync & Href & Pclk Defaut configuration : Vsync : 50Hz Href ~16.8 Khz Pclk 4.475Mhz
CanAdressGen COUNTER_GEN : process( hcount_reg, hinc_reg, hinc_next, vinc_reg ) begin hcount_next <= hcount_reg; if ( hinc_reg = '0' ) then hcount_next <= (others=>'0'); else hcount_next <= hcount_reg + 1 ; end if ; end process ; COUNTER2_GEN : process( vcount_reg,vinc_reg,vinc_next,hinc_reg,hinc_next ) begin vcount_next <= vcount_reg; if ( vinc_reg = '1' ) then vcount_next <= (others=>'0'); elsif( hinc_reg = '0' and hinc_next = '1') then vcount_next <= vcount_reg + 1 ; end if ; end process ;
Controls Signal : Cam domain ram_we1 <= '1' when vcount_reg < 64 and hcount_reg < 64 else '0'; ram_addr1<= vcount_reg (5 downto 0) & hcount_reg(5 downto 0); 64 64 ,[object Object],[object Object],[object Object],[object Object],288 352 pixel save pixel don’t save
Controls Signal : VGA domain ram_addr2 <= pixel_row(5 downto 0) & pixel_column(5 downto 0); valid <= '1' when pixel_row < 64 and pixel_column <64 else '0'; 64 64 480 640 ,[object Object],[object Object],pixel on pixel off
I/O Pin Assignments NET red_out<0> LOC = D6; NET red_out<1> LOC = C6; NET red_out<2> LOC = B6; NET red_out<3> LOC = D5; NET red_out<4> LOC = A5; NET red_out<5> LOC = B5; NET red_out<6> LOC = C5; NET red_out<7> LOC = B4; NET blue_out<0> LOC = E9; NET blue_out<1> LOC = F9; NET blue_out<2> LOC = D7; NET blue_out<3> LOC = C7; NET blue_out<4> LOC = E7; NET blue_out<5> LOC = F7; NET blue_out<6> LOC = E6; NET blue_out<7> LOC = F6; # VGA clock & reset NET clk_25mhz LOC = B11 ; NET horiz_sync_out LOC = E11; NET vert_sync_out LOC = D11; NET blank_out LOC = A4 ; NET csync_out LOC = A3 ; NET green_out<0> LOC = F10; NET green_out<1> LOC = D10; NET green_out<2> LOC = A10; NET green_out<3> LOC = D9; NET green_out<4> LOC = A9; NET green_out<5> LOC = B9; NET green_out<6> LOC = A8; NET green_out<7> LOC = B8; # cam signal NET cam_pclk LOC=AA12; NET cam_hsyn LOC = D2 ; NET cam_vsyn LOC = E3 ; #NET cam_rst LOC = E2 ; NET cam_Y<0> LOC = V3; NET cam_Y<1> LOC = U5; NET cam_Y<2> LOC = T5; NET cam_Y<3> LOC = V1; NET cam_Y<5> LOC = T2; NET cam_Y<4> LOC = U4; NET cam_Y<6> LOC = N4; NET cam_Y<7> LOC = U3;
Upgrading ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
keyPS2controller ram_dual Dual Port RAM font_rom vga_sync counter ctr D1 Q1 adrs1 adrs2 we1 Port A Port B inc dec ack data_ready back_space pixel_data kb_data cur _position Index_char curent_char kbdata kbclk exp3 : Keyboard (PS2) To VGA green blue red vert_sync horiz_sync

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VGA VHDL RTL design tutorial

  • 1. VGA - Display Example 1: Diagonal line display Example 2: Cam To VGA Example 3: Keyboard to VGA by Nabil CHOUBA
  • 3. Sync signal horizontal sync vertical sync
  • 4. DB15 connector DAC ! RGB Color 000 black 001 blue 010 green 011 cyan 100 red 101 magenta 110 yellow 111 white
  • 5.
  • 6.
  • 7. horizontal sync 640 660 756 800 Front porch TFP Back porch TBP Pulse width TPW
  • 8. vertical sync 480 494 495 525 Front porch TFP Back porch TBP Pulse width TPW
  • 9.
  • 10.
  • 11. VGA sync generation -- generate video on screen signals for pixel data video_on_h <= '1' when (h_count_reg <= 639) else '0'; video_on_v <= '1' when (v_count_reg <= 479) else '0'; -- video_on is high only when rgb data is displayed video_on <= video_on_h and video_on_v; cloked_process : process( clk_25mhz, rst ) begin if( rst='1' ) then h_count_reg <= (others=>'0') ; v_count_reg <= (others=>'0') ; elsif( clk_25mhz'event and clk_25mhz='1' ) then h_count_reg <= h_count_next; v_count_reg <= v_count_next; end if; end process ;
  • 12. Elementary graphics card sync generation counters pixel RAM or / and pixel generator row col 25MHz clock R G B hsync vsync BinData to display or / and OpenGL instruction Vedio_on
  • 13.
  • 14.
  • 15. vga_sync CanAdressGen Vsyn Hsyc pixel_data cam_Y Pixel_adrs green blue red vert_sync horiz_sync clk_25mhz clk_cam VGA Screen OmniVision OV6620 CMOS image sensor. exp2 : Cam To VGA cam_Y Size :352x288 Pclk2 :4.4M Size :640x480 Pclk1 :25M ram_dual Dual Port RAM D1 Q1 adrs1 adrs2 we1 Port A Port B clk2 clk1
  • 16. Dual Port RAM coding style entity ram_dual is generic( d_width : integer ; addr_width : integer ; mem_depth : integer ); port ( o2 : out STD_LOGIC_VECTOR(d_width - 1 downto 0); we1 : in STD_LOGIC; clk1 : in STD_LOGIC; d1 : in STD_LOGIC_VECTOR(d_width - 1 downto 0); addr1 : in unsigned(addr_width - 1 downto 0); clk2 : in STD_LOGIC; addr2 : in unsigned(addr_width - 1 downto 0) ); end ram_dual; architecture RAM_dual_arch of ram_dual is type mem_type is array (mem_depth - 1 downto 0) of STD_LOGIC_VECTOR (d_width - 1 downto 0); signal mem : mem_type; ram_dual Dual Port RAM D1 Q1 adrs1 adrs2 we1 Port A Port B clk2 clk1
  • 17.
  • 18.
  • 19. Vsync & Href & Pclk Defaut configuration : Vsync : 50Hz Href ~16.8 Khz Pclk 4.475Mhz
  • 20. CanAdressGen COUNTER_GEN : process( hcount_reg, hinc_reg, hinc_next, vinc_reg ) begin hcount_next <= hcount_reg; if ( hinc_reg = '0' ) then hcount_next <= (others=>'0'); else hcount_next <= hcount_reg + 1 ; end if ; end process ; COUNTER2_GEN : process( vcount_reg,vinc_reg,vinc_next,hinc_reg,hinc_next ) begin vcount_next <= vcount_reg; if ( vinc_reg = '1' ) then vcount_next <= (others=>'0'); elsif( hinc_reg = '0' and hinc_next = '1') then vcount_next <= vcount_reg + 1 ; end if ; end process ;
  • 21.
  • 22.
  • 23. I/O Pin Assignments NET red_out<0> LOC = D6; NET red_out<1> LOC = C6; NET red_out<2> LOC = B6; NET red_out<3> LOC = D5; NET red_out<4> LOC = A5; NET red_out<5> LOC = B5; NET red_out<6> LOC = C5; NET red_out<7> LOC = B4; NET blue_out<0> LOC = E9; NET blue_out<1> LOC = F9; NET blue_out<2> LOC = D7; NET blue_out<3> LOC = C7; NET blue_out<4> LOC = E7; NET blue_out<5> LOC = F7; NET blue_out<6> LOC = E6; NET blue_out<7> LOC = F6; # VGA clock & reset NET clk_25mhz LOC = B11 ; NET horiz_sync_out LOC = E11; NET vert_sync_out LOC = D11; NET blank_out LOC = A4 ; NET csync_out LOC = A3 ; NET green_out<0> LOC = F10; NET green_out<1> LOC = D10; NET green_out<2> LOC = A10; NET green_out<3> LOC = D9; NET green_out<4> LOC = A9; NET green_out<5> LOC = B9; NET green_out<6> LOC = A8; NET green_out<7> LOC = B8; # cam signal NET cam_pclk LOC=AA12; NET cam_hsyn LOC = D2 ; NET cam_vsyn LOC = E3 ; #NET cam_rst LOC = E2 ; NET cam_Y<0> LOC = V3; NET cam_Y<1> LOC = U5; NET cam_Y<2> LOC = T5; NET cam_Y<3> LOC = V1; NET cam_Y<5> LOC = T2; NET cam_Y<4> LOC = U4; NET cam_Y<6> LOC = N4; NET cam_Y<7> LOC = U3;
  • 24.
  • 25. keyPS2controller ram_dual Dual Port RAM font_rom vga_sync counter ctr D1 Q1 adrs1 adrs2 we1 Port A Port B inc dec ack data_ready back_space pixel_data kb_data cur _position Index_char curent_char kbdata kbclk exp3 : Keyboard (PS2) To VGA green blue red vert_sync horiz_sync