1. Time-driven reconfiguration-aware floorplacer BY Alessio Montone [email_address] Thesis committee: S. Dutt (chair), A. Khokhar, M.D. Santambrogio UIC Thesis Defense: 05/08/2008

5. INTRODUCTION

13. FLOORPLACEMENT

14. Floorplanning vs. Placement Placement Floor plan Characteristic Floorplanning Placement # items <100 >10.000 Items (for FPGAs) IP-Core Slice, CLB Aim Find a position for each item obj. function depends mainly on Area mainly on Wirelength Constraints Items can be positioned everywhere There is a set of possible positions

18. THE PROPOSED APPROACH

21. Input

22. Proposed Approach: overview

29. 2 nd Algorithm:TFiRR - VI

30. 2 nd Algorithm: TFiRR – Example

33. 3 rd Algorithm: RR floorplacement – Example - I

34. 3 rd Algorithm: RR floorplacement – Example - II

37. EXPERIMENTAL RESULTS

38. Identification of the number of RRs

42. COMPARISON WITH THE STATE OF THE ART

43. State of the art Authors Comm. Infrastructure Resource Aware Reconfiguration Aware Device Limits Aware Bazargan et al. No No Yes No Yuh et al. Limited, w/ High Overhead No Yes Yes Singhal et al. No No Yes No Feng et al. No Yes No No

52. Questions