SlideShare une entreprise Scribd logo

Intel Xeon Pre-Silicon Validation: Introduction and Challenges

•
•
D
DVClub
Technologie
1  sur  10
Télécharger pour lire hors ligne
Intel Xeon Pre-Silicon Validation Introduction & Challenges Paul Zehr December 5, 2006
2 Agenda This talk is intended to be an intro to Xeon pre- silicon validation work & challenges: Please stop me & ask questions Introduction • What is a “typical” Xeon processor Challenges • Re-Use • Some managerial issues • The usual…
3 What is a Xeon Processor? Silicon Processor Core Processor Cores Processor Cores Cache… Power-related New Technologies… Can be anything from a simple cache size increase to full blown from-scratch development of features RAS
4 Parameters Driving Xeon Validation TTM is the key driving factor • Quick ramp time new features need comprehending quickly Relatively “small” teams Validation “dominates” wrt team size • Bonus: high demand for talented DV engineers Focus is on what’s new & changed • Still need to validate full chip • Beware: minor design changes can have broad impact Heavy re-use of other design environments • Combining environments always sounds easier at proj. conception… Tend to be cross-site efforts Trend: More & more from-scratch design being added
5 Challenges: Re-Use First, a few examples: • Merced’s bus cluster • Whitefield Expectation is that gluing various pieces of design together is fast & easy • State of the “parent” design can be an issue… Varying design languages / environments A lot of code implemented for “single use” • Poorly written code from parent projects • Never intended to be proliferated in the first place Engineers need to understand original intent Re-use of unfinished code
6 Challenges: Managerial Influence of validation on project design during concept phase • Stop feature creep at the source… • “simple” arch deltas can cause inordinate validation Cross-site teams Documentation & training from parent project(s) Retention • Need experienced teams to meet goals, but, • Also need development challenges to retain…
7 Challenges: The Usual Model Size & Speed • Emulation & Formal help, but… • Speed exacerbated by ever-growing number of clock domains • Ever-increasing sets of tools doesn’t help either Emulation: • Long initial RTL model build time (months). • Less granular checking • Debug requires extra steps • Not a real effective way to get out early bugs. Formal for specific areas, but isn’t mature • Meaning: We still simulate everything
8 Challenges (cont.) Stimulus: We tend to be very repetitive: • “Start-Up” code is almost identical for 1000’s of tests • RIT example: S/W semaphores (or barriers) & interrupt handlers – Many RIT generators code “macros” – same code each time – Some people have gotten creative here, but needs more • Challenge is to minimize duplicate code – especially in the large bug-hunting runs. Checking: Escapes rarely due to lack of checking • Checker overhead still an issue – Code ‘em into RTL – helps emulation as well – Could aid in post-Si debug if done properly Coverage: Again, adds overhead to the model • A lot of philosophical differences here – internally & externally… • Need better solutions with less overhead – See checking. Debug: Vendors need to understand varying needs • Large, monolithic all-in-one solutions don’t suit all
9 A bit more on stimulus & coverage Low % Covered ~100 % Covered
10 Challenges (cont.) Cross over between pre & post Si • Portability of tests between post & pre silicon – Implications on environment • Circuits/phys. design & implementation need functional tests to find timing & noise – Intent verification requires ability to run on pre-si models

Recommandé

Pre-Si Verification for Post-Si Validation
Pre-Si Verification for Post-Si ValidationPre-Si Verification for Post-Si Validation
Pre-Si Verification for Post-Si ValidationDVClub
 
basic vlsi ppt
basic vlsi pptbasic vlsi ppt
basic vlsi pptSidduzalaki143
 
Mos transistor theory
Mos transistor theoryMos transistor theory
Mos transistor theoryEkta Jolly
 
VLSI Technology
VLSI TechnologyVLSI Technology
VLSI TechnologyHasib Hossen
 
Michael john sebastian smith application-specific integrated circuits-addison...
Michael john sebastian smith application-specific integrated circuits-addison...Michael john sebastian smith application-specific integrated circuits-addison...
Michael john sebastian smith application-specific integrated circuits-addison...Đình Khanh Nguyễn
 
Clock Skew 2
Clock Skew 2Clock Skew 2
Clock Skew 2rchovatiya
 
Crosstalk
CrosstalkCrosstalk
CrosstalkManikanta Gogula
 
CMOS
CMOS CMOS
CMOS AWANISHKUMAR84
 

Recommandé

Pre-Si Verification for Post-Si Validation
Pre-Si Verification for Post-Si ValidationPre-Si Verification for Post-Si Validation
Pre-Si Verification for Post-Si ValidationDVClub
 
basic vlsi ppt
basic vlsi pptbasic vlsi ppt
basic vlsi pptSidduzalaki143
 
Mos transistor theory
Mos transistor theoryMos transistor theory
Mos transistor theoryEkta Jolly
 
VLSI Technology
VLSI TechnologyVLSI Technology
VLSI TechnologyHasib Hossen
 
Michael john sebastian smith application-specific integrated circuits-addison...
Michael john sebastian smith application-specific integrated circuits-addison...Michael john sebastian smith application-specific integrated circuits-addison...
Michael john sebastian smith application-specific integrated circuits-addison...Đình Khanh Nguyễn
 
Clock Skew 2
Clock Skew 2Clock Skew 2
Clock Skew 2rchovatiya
 
Crosstalk
CrosstalkCrosstalk
CrosstalkManikanta Gogula
 
CMOS
CMOS CMOS
CMOS AWANISHKUMAR84
 
Adder
Adder Adder
Adder anuppatel111
 
Basics Of VLSI
Basics Of VLSIBasics Of VLSI
Basics Of VLSIAvanish Agarwal
 
Vlsi design 11
Vlsi design 11Vlsi design 11
Vlsi design 11HIMANSHU DIWAKAR
 
CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...
CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...
CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...rameshreddybattini
 
Chapter 3 instruction set-of-8085
Chapter 3 instruction set-of-8085Chapter 3 instruction set-of-8085
Chapter 3 instruction set-of-8085Shubham Singh
 
Vlsi design
Vlsi designVlsi design
Vlsi designIftikar Alam
 
Introduction to HDLs
Introduction to HDLsIntroduction to HDLs
Introduction to HDLsIndiraPriyadarshini30
 
Book Preview: A Practical Introduction to the Xilinx Zynq-7000 Adaptive SoC
Book Preview: A Practical Introduction to the Xilinx Zynq-7000 Adaptive SoCBook Preview: A Practical Introduction to the Xilinx Zynq-7000 Adaptive SoC
Book Preview: A Practical Introduction to the Xilinx Zynq-7000 Adaptive SoCDerek Murray
 
ARM® Cortex M Boot & CMSIS Part 1-3
ARM® Cortex M Boot & CMSIS Part 1-3ARM® Cortex M Boot & CMSIS Part 1-3
ARM® Cortex M Boot & CMSIS Part 1-3Raahul Raghavan
 
Verilog HDL
Verilog HDL Verilog HDL
Verilog HDL HasmukhPKoringa
 
finfet tsmc.pdf
finfet tsmc.pdffinfet tsmc.pdf
finfet tsmc.pdfMANSISHEKHAWAT3
 
Analog vlsi
Analog vlsiAnalog vlsi
Analog vlsiKhuong Lamborghini
 
Study of vlsi design methodologies and limitations using cad tools for cmos t...
Study of vlsi design methodologies and limitations using cad tools for cmos t...Study of vlsi design methodologies and limitations using cad tools for cmos t...
Study of vlsi design methodologies and limitations using cad tools for cmos t...Lakshmi Narain College of Technology & Science Bhopal
 
Digital Electronics Fundamentals
Digital Electronics Fundamentals Digital Electronics Fundamentals
Digital Electronics Fundamentals Darwin Nesakumar
 
PCB designing and tools
PCB designing and toolsPCB designing and tools
PCB designing and toolsAkash Jadhav
 
Spartan-II FPGA (xc2s30)
Spartan-II FPGA (xc2s30)Spartan-II FPGA (xc2s30)
Spartan-II FPGA (xc2s30)A B Shinde
 
GUI for DRV fix in ICC2
GUI for DRV fix in ICC2GUI for DRV fix in ICC2
GUI for DRV fix in ICC2Prashanth Chokkarapu
 
VLSI Design-Lecture2 introduction to ic technology
VLSI Design-Lecture2 introduction to ic technologyVLSI Design-Lecture2 introduction to ic technology
VLSI Design-Lecture2 introduction to ic technologysritulasiadigopula
 
Physical Verification Design.pdf
Physical Verification Design.pdfPhysical Verification Design.pdf
Physical Verification Design.pdfAhmed Abdelazeem
 
History of microprocessors copy
History of microprocessors copyHistory of microprocessors copy
History of microprocessors copyyvonne katsande
 
OOP for Hardware Verification--Demystified!
OOP for Hardware Verification--Demystified! OOP for Hardware Verification--Demystified!
OOP for Hardware Verification--Demystified! DVClub
 
SystemVerilog OOP Ovm Features Summary
SystemVerilog OOP Ovm Features SummarySystemVerilog OOP Ovm Features Summary
SystemVerilog OOP Ovm Features SummaryAmal Khailtash
 

Contenu connexe

Tendances

CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...
CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...
CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...rameshreddybattini
 
Chapter 3 instruction set-of-8085
Chapter 3 instruction set-of-8085Chapter 3 instruction set-of-8085
Chapter 3 instruction set-of-8085Shubham Singh
 
Book Preview: A Practical Introduction to the Xilinx Zynq-7000 Adaptive SoC
Book Preview: A Practical Introduction to the Xilinx Zynq-7000 Adaptive SoCBook Preview: A Practical Introduction to the Xilinx Zynq-7000 Adaptive SoC
Book Preview: A Practical Introduction to the Xilinx Zynq-7000 Adaptive SoCDerek Murray
 
ARM® Cortex M Boot & CMSIS Part 1-3
ARM® Cortex M Boot & CMSIS Part 1-3ARM® Cortex M Boot & CMSIS Part 1-3
ARM® Cortex M Boot & CMSIS Part 1-3Raahul Raghavan
 
Digital Electronics Fundamentals
Digital Electronics Fundamentals Digital Electronics Fundamentals
Digital Electronics Fundamentals Darwin Nesakumar
 
PCB designing and tools
PCB designing and toolsPCB designing and tools
PCB designing and toolsAkash Jadhav
 
Spartan-II FPGA (xc2s30)
Spartan-II FPGA (xc2s30)Spartan-II FPGA (xc2s30)
Spartan-II FPGA (xc2s30)A B Shinde
 
VLSI Design-Lecture2 introduction to ic technology
VLSI Design-Lecture2 introduction to ic technologyVLSI Design-Lecture2 introduction to ic technology
VLSI Design-Lecture2 introduction to ic technologysritulasiadigopula
 
Physical Verification Design.pdf
Physical Verification Design.pdfPhysical Verification Design.pdf
Physical Verification Design.pdfAhmed Abdelazeem
 
History of microprocessors copy
History of microprocessors copyHistory of microprocessors copy
History of microprocessors copyyvonne katsande
 

Tendances (20)

Adder
Adder Adder
Adder
 
Basics Of VLSI
Basics Of VLSIBasics Of VLSI
Basics Of VLSI
 
Vlsi design 11
Vlsi design 11Vlsi design 11
Vlsi design 11
 
CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...
CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...
CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIP...
 
Chapter 3 instruction set-of-8085
Chapter 3 instruction set-of-8085Chapter 3 instruction set-of-8085
Chapter 3 instruction set-of-8085
 
Vlsi design
Vlsi designVlsi design
Vlsi design
 
Introduction to HDLs
Introduction to HDLsIntroduction to HDLs
Introduction to HDLs
 
Book Preview: A Practical Introduction to the Xilinx Zynq-7000 Adaptive SoC
Book Preview: A Practical Introduction to the Xilinx Zynq-7000 Adaptive SoCBook Preview: A Practical Introduction to the Xilinx Zynq-7000 Adaptive SoC
Book Preview: A Practical Introduction to the Xilinx Zynq-7000 Adaptive SoC
 
ARM® Cortex M Boot & CMSIS Part 1-3
ARM® Cortex M Boot & CMSIS Part 1-3ARM® Cortex M Boot & CMSIS Part 1-3
ARM® Cortex M Boot & CMSIS Part 1-3
 
Verilog HDL
Verilog HDL Verilog HDL
Verilog HDL
 
finfet tsmc.pdf
finfet tsmc.pdffinfet tsmc.pdf
finfet tsmc.pdf
 
Analog vlsi
Analog vlsiAnalog vlsi
Analog vlsi
 
Study of vlsi design methodologies and limitations using cad tools for cmos t...
Study of vlsi design methodologies and limitations using cad tools for cmos t...Study of vlsi design methodologies and limitations using cad tools for cmos t...
Study of vlsi design methodologies and limitations using cad tools for cmos t...
 
Digital Electronics Fundamentals
Digital Electronics Fundamentals Digital Electronics Fundamentals
Digital Electronics Fundamentals
 
PCB designing and tools
PCB designing and toolsPCB designing and tools
PCB designing and tools
 
Spartan-II FPGA (xc2s30)
Spartan-II FPGA (xc2s30)Spartan-II FPGA (xc2s30)
Spartan-II FPGA (xc2s30)
 
GUI for DRV fix in ICC2
GUI for DRV fix in ICC2GUI for DRV fix in ICC2
GUI for DRV fix in ICC2
 
VLSI Design-Lecture2 introduction to ic technology
VLSI Design-Lecture2 introduction to ic technologyVLSI Design-Lecture2 introduction to ic technology
VLSI Design-Lecture2 introduction to ic technology
 
Physical Verification Design.pdf
Physical Verification Design.pdfPhysical Verification Design.pdf
Physical Verification Design.pdf
 
History of microprocessors copy
History of microprocessors copyHistory of microprocessors copy
History of microprocessors copy
 

En vedette

OOP for Hardware Verification--Demystified!
OOP for Hardware Verification--Demystified! OOP for Hardware Verification--Demystified!
OOP for Hardware Verification--Demystified! DVClub
 
SystemVerilog OOP Ovm Features Summary
SystemVerilog OOP Ovm Features SummarySystemVerilog OOP Ovm Features Summary
SystemVerilog OOP Ovm Features SummaryAmal Khailtash
 
Verification of Graphics ASICs (Part I)
Verification of Graphics ASICs (Part I)Verification of Graphics ASICs (Part I)
Verification of Graphics ASICs (Part I)DVClub
 
Verification of Graphics ASICs (Part II)
Verification of Graphics ASICs (Part II)Verification of Graphics ASICs (Part II)
Verification of Graphics ASICs (Part II)DVClub
 
AMD_11th_Intl_SoC_Conf_UCI_Irvine
AMD_11th_Intl_SoC_Conf_UCI_IrvineAMD_11th_Intl_SoC_Conf_UCI_Irvine
AMD_11th_Intl_SoC_Conf_UCI_IrvinePankaj Singh
 
Validating Next Generation CPUs
Validating Next Generation CPUsValidating Next Generation CPUs
Validating Next Generation CPUsDVClub
 
Low-Power Design and Verification
Low-Power Design and VerificationLow-Power Design and Verification
Low-Power Design and VerificationDVClub
 
Intel Atom Processor Pre-Silicon Verification Experience
Intel Atom Processor Pre-Silicon Verification ExperienceIntel Atom Processor Pre-Silicon Verification Experience
Intel Atom Processor Pre-Silicon Verification ExperienceDVClub
 
Efficiency Through Methodology
Efficiency Through MethodologyEfficiency Through Methodology
Efficiency Through MethodologyDVClub
 
UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design...
UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design...UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design...
UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design...shaotao liu
 
Approaches for Power Management Verification of SOC
Approaches for Power Management Verification of SOC Approaches for Power Management Verification of SOC
Approaches for Power Management Verification of SOC DVClub
 
Low Power Design flow using Power Format
Low Power Design flow using Power FormatLow Power Design flow using Power Format
Low Power Design flow using Power Formatijsrd.com
 
Low Power Design Verification of Complex Chips
Low Power Design Verification of Complex ChipsLow Power Design Verification of Complex Chips
Low Power Design Verification of Complex ChipsDVClub
 
2012EE10432_Abhishek_Lal
2012EE10432_Abhishek_Lal2012EE10432_Abhishek_Lal
2012EE10432_Abhishek_LalAbhishek Lal
 
UVM: Basic Sequences
UVM: Basic SequencesUVM: Basic Sequences
UVM: Basic SequencesArrow Devices
 
Functional verification techniques EW16 session
Functional verification techniques EW16 sessionFunctional verification techniques EW16 session
Functional verification techniques EW16 sessionSameh El-Ashry
 
Verification challenges and methodologies - SoC and ASICs
Verification challenges and methodologies - SoC and ASICsVerification challenges and methodologies - SoC and ASICs
Verification challenges and methodologies - SoC and ASICsDr. Shivananda Koteshwar
 
UVM Methodology Tutorial
UVM Methodology TutorialUVM Methodology Tutorial
UVM Methodology TutorialArrow Devices
 

En vedette (19)

OOP for Hardware Verification--Demystified!
OOP for Hardware Verification--Demystified! OOP for Hardware Verification--Demystified!
OOP for Hardware Verification--Demystified!
 
SystemVerilog OOP Ovm Features Summary
SystemVerilog OOP Ovm Features SummarySystemVerilog OOP Ovm Features Summary
SystemVerilog OOP Ovm Features Summary
 
Verification of Graphics ASICs (Part I)
Verification of Graphics ASICs (Part I)Verification of Graphics ASICs (Part I)
Verification of Graphics ASICs (Part I)
 
Verification of Graphics ASICs (Part II)
Verification of Graphics ASICs (Part II)Verification of Graphics ASICs (Part II)
Verification of Graphics ASICs (Part II)
 
AMD_11th_Intl_SoC_Conf_UCI_Irvine
AMD_11th_Intl_SoC_Conf_UCI_IrvineAMD_11th_Intl_SoC_Conf_UCI_Irvine
AMD_11th_Intl_SoC_Conf_UCI_Irvine
 
Validating Next Generation CPUs
Validating Next Generation CPUsValidating Next Generation CPUs
Validating Next Generation CPUs
 
Low-Power Design and Verification
Low-Power Design and VerificationLow-Power Design and Verification
Low-Power Design and Verification
 
Intel Atom Processor Pre-Silicon Verification Experience
Intel Atom Processor Pre-Silicon Verification ExperienceIntel Atom Processor Pre-Silicon Verification Experience
Intel Atom Processor Pre-Silicon Verification Experience
 
Efficiency Through Methodology
Efficiency Through MethodologyEfficiency Through Methodology
Efficiency Through Methodology
 
UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design...
UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design...UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design...
UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design...
 
Approaches for Power Management Verification of SOC
Approaches for Power Management Verification of SOC Approaches for Power Management Verification of SOC
Approaches for Power Management Verification of SOC
 
Low Power Design flow using Power Format
Low Power Design flow using Power FormatLow Power Design flow using Power Format
Low Power Design flow using Power Format
 
Low Power Design Verification of Complex Chips
Low Power Design Verification of Complex ChipsLow Power Design Verification of Complex Chips
Low Power Design Verification of Complex Chips
 
2012EE10432_Abhishek_Lal
2012EE10432_Abhishek_Lal2012EE10432_Abhishek_Lal
2012EE10432_Abhishek_Lal
 
UVM: Basic Sequences
UVM: Basic SequencesUVM: Basic Sequences
UVM: Basic Sequences
 
Functional verification techniques EW16 session
Functional verification techniques EW16 sessionFunctional verification techniques EW16 session
Functional verification techniques EW16 session
 
Verification challenges and methodologies - SoC and ASICs
Verification challenges and methodologies - SoC and ASICsVerification challenges and methodologies - SoC and ASICs
Verification challenges and methodologies - SoC and ASICs
 
UVM Methodology Tutorial
UVM Methodology TutorialUVM Methodology Tutorial
UVM Methodology Tutorial
 
Coverage and Introduction to UVM
Coverage and Introduction to UVMCoverage and Introduction to UVM
Coverage and Introduction to UVM
 

Similaire à Intel Xeon Pre-Silicon Validation: Introduction and Challenges

TDD and Related Techniques for Non Developers (2012)
TDD and Related Techniques for Non Developers (2012)TDD and Related Techniques for Non Developers (2012)
TDD and Related Techniques for Non Developers (2012)Peter Kofler
 
Project Sherpa: How RightScale Went All in on Docker
Project Sherpa: How RightScale Went All in on DockerProject Sherpa: How RightScale Went All in on Docker
Project Sherpa: How RightScale Went All in on DockerRightScale
 
Lessons Learned Replatforming A Large Machine Learning Application To Apache ...
Lessons Learned Replatforming A Large Machine Learning Application To Apache ...Lessons Learned Replatforming A Large Machine Learning Application To Apache ...
Lessons Learned Replatforming A Large Machine Learning Application To Apache ...Databricks
 
The View - 30 proven Lotuscript tips
The View - 30 proven Lotuscript tipsThe View - 30 proven Lotuscript tips
The View - 30 proven Lotuscript tipsBill Buchan
 
How to test a Mainframe Application
How to test a Mainframe ApplicationHow to test a Mainframe Application
How to test a Mainframe ApplicationMichael Erichsen
 
Performance Optimization of Cloud Based Applications by Peter Smith, ACL
Performance Optimization of Cloud Based Applications by Peter Smith, ACLPerformance Optimization of Cloud Based Applications by Peter Smith, ACL
Performance Optimization of Cloud Based Applications by Peter Smith, ACLTriNimbus
 
Test driven development v1.0
Test driven development v1.0Test driven development v1.0
Test driven development v1.0Ganesh Kondal
 
Scaling a High Traffic Web Application: Our Journey from Java to PHP
Scaling a High Traffic Web Application: Our Journey from Java to PHPScaling a High Traffic Web Application: Our Journey from Java to PHP
Scaling a High Traffic Web Application: Our Journey from Java to PHP120bi
 
Scaling High Traffic Web Applications
Scaling High Traffic Web ApplicationsScaling High Traffic Web Applications
Scaling High Traffic Web ApplicationsAchievers Tech
 
Dev buchan 30 proven tips
Dev buchan 30 proven tipsDev buchan 30 proven tips
Dev buchan 30 proven tipsBill Buchan
 
Get Testing with tSQLt - SQL In The City Workshop 2014
Get Testing with tSQLt - SQL In The City Workshop 2014Get Testing with tSQLt - SQL In The City Workshop 2014
Get Testing with tSQLt - SQL In The City Workshop 2014Red Gate Software
 
PAC 2019 virtual Alexander Podelko
PAC 2019 virtual Alexander Podelko PAC 2019 virtual Alexander Podelko
PAC 2019 virtual Alexander Podelko Neotys
 
Delphix and DBmaestro
Delphix and DBmaestroDelphix and DBmaestro
Delphix and DBmaestroKyle Hailey
 
The View - Lotusscript coding best practices
The View - Lotusscript coding best practicesThe View - Lotusscript coding best practices
The View - Lotusscript coding best practicesBill Buchan
 
Make It Cooler: Using Decentralized Version Control
Make It Cooler: Using Decentralized Version ControlMake It Cooler: Using Decentralized Version Control
Make It Cooler: Using Decentralized Version Controlindiver
 
Unit Testing Best Practices
Unit Testing Best PracticesUnit Testing Best Practices
Unit Testing Best PracticesTomaš Maconko
 

Similaire à Intel Xeon Pre-Silicon Validation: Introduction and Challenges (20)

Zehr dv club_12052006
Zehr dv club_12052006Zehr dv club_12052006
Zehr dv club_12052006
 
TDD and Related Techniques for Non Developers (2012)
TDD and Related Techniques for Non Developers (2012)TDD and Related Techniques for Non Developers (2012)
TDD and Related Techniques for Non Developers (2012)
 
Project Sherpa: How RightScale Went All in on Docker
Project Sherpa: How RightScale Went All in on DockerProject Sherpa: How RightScale Went All in on Docker
Project Sherpa: How RightScale Went All in on Docker
 
DevOps 101
DevOps 101DevOps 101
DevOps 101
 
Lessons Learned Replatforming A Large Machine Learning Application To Apache ...
Lessons Learned Replatforming A Large Machine Learning Application To Apache ...Lessons Learned Replatforming A Large Machine Learning Application To Apache ...
Lessons Learned Replatforming A Large Machine Learning Application To Apache ...
 
The View - 30 proven Lotuscript tips
The View - 30 proven Lotuscript tipsThe View - 30 proven Lotuscript tips
The View - 30 proven Lotuscript tips
 
How to test a Mainframe Application
How to test a Mainframe ApplicationHow to test a Mainframe Application
How to test a Mainframe Application
 
Performance Optimization of Cloud Based Applications by Peter Smith, ACL
Performance Optimization of Cloud Based Applications by Peter Smith, ACLPerformance Optimization of Cloud Based Applications by Peter Smith, ACL
Performance Optimization of Cloud Based Applications by Peter Smith, ACL
 
Test driven development v1.0
Test driven development v1.0Test driven development v1.0
Test driven development v1.0
 
Scaling a High Traffic Web Application: Our Journey from Java to PHP
Scaling a High Traffic Web Application: Our Journey from Java to PHPScaling a High Traffic Web Application: Our Journey from Java to PHP
Scaling a High Traffic Web Application: Our Journey from Java to PHP
 
Scaling High Traffic Web Applications
Scaling High Traffic Web ApplicationsScaling High Traffic Web Applications
Scaling High Traffic Web Applications
 
Dev buchan 30 proven tips
Dev buchan 30 proven tipsDev buchan 30 proven tips
Dev buchan 30 proven tips
 
Get Testing with tSQLt - SQL In The City Workshop 2014
Get Testing with tSQLt - SQL In The City Workshop 2014Get Testing with tSQLt - SQL In The City Workshop 2014
Get Testing with tSQLt - SQL In The City Workshop 2014
 
CNUG TDD June 2014
CNUG TDD June 2014CNUG TDD June 2014
CNUG TDD June 2014
 
PAC 2019 virtual Alexander Podelko
PAC 2019 virtual Alexander Podelko PAC 2019 virtual Alexander Podelko
PAC 2019 virtual Alexander Podelko
 
Delphix and DBmaestro
Delphix and DBmaestroDelphix and DBmaestro
Delphix and DBmaestro
 
The View - Lotusscript coding best practices
The View - Lotusscript coding best practicesThe View - Lotusscript coding best practices
The View - Lotusscript coding best practices
 
Make It Cooler: Using Decentralized Version Control
Make It Cooler: Using Decentralized Version ControlMake It Cooler: Using Decentralized Version Control
Make It Cooler: Using Decentralized Version Control
 
Unit Testing Best Practices
Unit Testing Best PracticesUnit Testing Best Practices
Unit Testing Best Practices
 
Intro to TDD
Intro to TDDIntro to TDD
Intro to TDD
 

Plus de DVClub

IP Reuse Impact on Design Verification Management Across the Enterprise
IP Reuse Impact on Design Verification Management Across the EnterpriseIP Reuse Impact on Design Verification Management Across the Enterprise
IP Reuse Impact on Design Verification Management Across the EnterpriseDVClub
 
Cisco Base Environment Overview
Cisco Base Environment OverviewCisco Base Environment Overview
Cisco Base Environment OverviewDVClub
 
Stop Writing Assertions! Efficient Verification Methodology
Stop Writing Assertions! Efficient Verification MethodologyStop Writing Assertions! Efficient Verification Methodology
Stop Writing Assertions! Efficient Verification MethodologyDVClub
 
Verification Automation Using IPXACT
Verification Automation Using IPXACTVerification Automation Using IPXACT
Verification Automation Using IPXACTDVClub
 
Validation and Design in a Small Team Environment
Validation and Design in a Small Team EnvironmentValidation and Design in a Small Team Environment
Validation and Design in a Small Team EnvironmentDVClub
 
Trends in Mixed Signal Validation
Trends in Mixed Signal ValidationTrends in Mixed Signal Validation
Trends in Mixed Signal ValidationDVClub
 
Verification In A Global Design Community
Verification In A Global Design CommunityVerification In A Global Design Community
Verification In A Global Design CommunityDVClub
 
Design Verification Using SystemC
Design Verification Using SystemCDesign Verification Using SystemC
Design Verification Using SystemCDVClub
 
Verification Strategy for PCI-Express
Verification Strategy for PCI-ExpressVerification Strategy for PCI-Express
Verification Strategy for PCI-ExpressDVClub
 
SystemVerilog Assertions (SVA) in the Design/Verification Process
SystemVerilog Assertions (SVA) in the Design/Verification ProcessSystemVerilog Assertions (SVA) in the Design/Verification Process
SystemVerilog Assertions (SVA) in the Design/Verification ProcessDVClub
 
OpenSPARC T1 Processor
OpenSPARC T1 ProcessorOpenSPARC T1 Processor
OpenSPARC T1 ProcessorDVClub
 
Using Assertions in AMS Verification
Using Assertions in AMS VerificationUsing Assertions in AMS Verification
Using Assertions in AMS VerificationDVClub
 
UVM Update: Register Package
UVM Update: Register PackageUVM Update: Register Package
UVM Update: Register PackageDVClub
 
Verification of the QorIQ Communication Platform Containing CoreNet Fabric wi...
Verification of the QorIQ Communication Platform Containing CoreNet Fabric wi...Verification of the QorIQ Communication Platform Containing CoreNet Fabric wi...
Verification of the QorIQ Communication Platform Containing CoreNet Fabric wi...DVClub
 
Verification of Wireless SoCs: No Longer in the Dark Ages
Verification of Wireless SoCs: No Longer in the Dark AgesVerification of Wireless SoCs: No Longer in the Dark Ages
Verification of Wireless SoCs: No Longer in the Dark AgesDVClub
 
I Never Thought I Would Grow Up to be This Formal
I Never Thought I Would Grow Up to be This FormalI Never Thought I Would Grow Up to be This Formal
I Never Thought I Would Grow Up to be This FormalDVClub
 
OMAP Verification
OMAP VerificationOMAP Verification
OMAP VerificationDVClub
 
Roy aeroVerifying Power Domains in AeroFONE
Roy aeroVerifying Power Domains in AeroFONERoy aeroVerifying Power Domains in AeroFONE
Roy aeroVerifying Power Domains in AeroFONEDVClub
 
Challenges in Using UVM at SoC Level
Challenges in Using UVM at SoC LevelChallenges in Using UVM at SoC Level
Challenges in Using UVM at SoC LevelDVClub
 
Advanced Methodologies Used for Top-Level Verification of Mixed Signal Products
Advanced Methodologies Used for Top-Level Verification of Mixed Signal ProductsAdvanced Methodologies Used for Top-Level Verification of Mixed Signal Products
Advanced Methodologies Used for Top-Level Verification of Mixed Signal ProductsDVClub
 

Plus de DVClub (20)

IP Reuse Impact on Design Verification Management Across the Enterprise
IP Reuse Impact on Design Verification Management Across the EnterpriseIP Reuse Impact on Design Verification Management Across the Enterprise
IP Reuse Impact on Design Verification Management Across the Enterprise
 
Cisco Base Environment Overview
Cisco Base Environment OverviewCisco Base Environment Overview
Cisco Base Environment Overview
 
Stop Writing Assertions! Efficient Verification Methodology
Stop Writing Assertions! Efficient Verification MethodologyStop Writing Assertions! Efficient Verification Methodology
Stop Writing Assertions! Efficient Verification Methodology
 
Verification Automation Using IPXACT
Verification Automation Using IPXACTVerification Automation Using IPXACT
Verification Automation Using IPXACT
 
Validation and Design in a Small Team Environment
Validation and Design in a Small Team EnvironmentValidation and Design in a Small Team Environment
Validation and Design in a Small Team Environment
 
Trends in Mixed Signal Validation
Trends in Mixed Signal ValidationTrends in Mixed Signal Validation
Trends in Mixed Signal Validation
 
Verification In A Global Design Community
Verification In A Global Design CommunityVerification In A Global Design Community
Verification In A Global Design Community
 
Design Verification Using SystemC
Design Verification Using SystemCDesign Verification Using SystemC
Design Verification Using SystemC
 
Verification Strategy for PCI-Express
Verification Strategy for PCI-ExpressVerification Strategy for PCI-Express
Verification Strategy for PCI-Express
 
SystemVerilog Assertions (SVA) in the Design/Verification Process
SystemVerilog Assertions (SVA) in the Design/Verification ProcessSystemVerilog Assertions (SVA) in the Design/Verification Process
SystemVerilog Assertions (SVA) in the Design/Verification Process
 
OpenSPARC T1 Processor
OpenSPARC T1 ProcessorOpenSPARC T1 Processor
OpenSPARC T1 Processor
 
Using Assertions in AMS Verification
Using Assertions in AMS VerificationUsing Assertions in AMS Verification
Using Assertions in AMS Verification
 
UVM Update: Register Package
UVM Update: Register PackageUVM Update: Register Package
UVM Update: Register Package
 
Verification of the QorIQ Communication Platform Containing CoreNet Fabric wi...
Verification of the QorIQ Communication Platform Containing CoreNet Fabric wi...Verification of the QorIQ Communication Platform Containing CoreNet Fabric wi...
Verification of the QorIQ Communication Platform Containing CoreNet Fabric wi...
 
Verification of Wireless SoCs: No Longer in the Dark Ages
Verification of Wireless SoCs: No Longer in the Dark AgesVerification of Wireless SoCs: No Longer in the Dark Ages
Verification of Wireless SoCs: No Longer in the Dark Ages
 
I Never Thought I Would Grow Up to be This Formal
I Never Thought I Would Grow Up to be This FormalI Never Thought I Would Grow Up to be This Formal
I Never Thought I Would Grow Up to be This Formal
 
OMAP Verification
OMAP VerificationOMAP Verification
OMAP Verification
 
Roy aeroVerifying Power Domains in AeroFONE
Roy aeroVerifying Power Domains in AeroFONERoy aeroVerifying Power Domains in AeroFONE
Roy aeroVerifying Power Domains in AeroFONE
 
Challenges in Using UVM at SoC Level
Challenges in Using UVM at SoC LevelChallenges in Using UVM at SoC Level
Challenges in Using UVM at SoC Level
 
Advanced Methodologies Used for Top-Level Verification of Mixed Signal Products
Advanced Methodologies Used for Top-Level Verification of Mixed Signal ProductsAdvanced Methodologies Used for Top-Level Verification of Mixed Signal Products
Advanced Methodologies Used for Top-Level Verification of Mixed Signal Products
 

Dernier

Exploring the Future Potential of AI-Enabled Smartphone Processors
Exploring the Future Potential of AI-Enabled Smartphone ProcessorsExploring the Future Potential of AI-Enabled Smartphone Processors
Exploring the Future Potential of AI-Enabled Smartphone Processorsdebabhi2
 
08448380779 Call Girls In Civil Lines Women Seeking Men
08448380779 Call Girls In Civil Lines Women Seeking Men08448380779 Call Girls In Civil Lines Women Seeking Men
08448380779 Call Girls In Civil Lines Women Seeking MenDelhi Call girls
 
Top 5 Benefits OF Using Muvi Live Paywall For Live Streams
Top 5 Benefits OF Using Muvi Live Paywall For Live StreamsTop 5 Benefits OF Using Muvi Live Paywall For Live Streams
Top 5 Benefits OF Using Muvi Live Paywall For Live StreamsRoshan Dwivedi
 
How to convert PDF to text with Nanonets
How to convert PDF to text with NanonetsHow to convert PDF to text with Nanonets
How to convert PDF to text with Nanonetsnaman860154
 
Neo4j - How KGs are shaping the future of Generative AI at AWS Summit London ...
Neo4j - How KGs are shaping the future of Generative AI at AWS Summit London ...Neo4j - How KGs are shaping the future of Generative AI at AWS Summit London ...
Neo4j - How KGs are shaping the future of Generative AI at AWS Summit London ...Neo4j
 
2024: Domino Containers - The Next Step. News from the Domino Container commu...
2024: Domino Containers - The Next Step. News from the Domino Container commu...2024: Domino Containers - The Next Step. News from the Domino Container commu...
2024: Domino Containers - The Next Step. News from the Domino Container commu...Martijn de Jong
 
Driving Behavioral Change for Information Management through Data-Driven Gree...
Driving Behavioral Change for Information Management through Data-Driven Gree...Driving Behavioral Change for Information Management through Data-Driven Gree...
Driving Behavioral Change for Information Management through Data-Driven Gree...Enterprise Knowledge
 
04-2024-HHUG-Sales-and-Marketing-Alignment.pptx
04-2024-HHUG-Sales-and-Marketing-Alignment.pptx04-2024-HHUG-Sales-and-Marketing-Alignment.pptx
04-2024-HHUG-Sales-and-Marketing-Alignment.pptxHampshireHUG
 
Apidays Singapore 2024 - Building Digital Trust in a Digital Economy by Veron...
Apidays Singapore 2024 - Building Digital Trust in a Digital Economy by Veron...Apidays Singapore 2024 - Building Digital Trust in a Digital Economy by Veron...
Apidays Singapore 2024 - Building Digital Trust in a Digital Economy by Veron...apidays
 
Automating Google Workspace (GWS) & more with Apps Script
Automating Google Workspace (GWS) & more with Apps ScriptAutomating Google Workspace (GWS) & more with Apps Script
Automating Google Workspace (GWS) & more with Apps Scriptwesley chun
 
Histor y of HAM Radio presentation slide
Histor y of HAM Radio presentation slideHistor y of HAM Radio presentation slide
Histor y of HAM Radio presentation slidevu2urc
 
[2024]Digital Global Overview Report 2024 Meltwater.pdf
[2024]Digital Global Overview Report 2024 Meltwater.pdf[2024]Digital Global Overview Report 2024 Meltwater.pdf
[2024]Digital Global Overview Report 2024 Meltwater.pdfhans926745
 
Slack Application Development 101 Slides
Slack Application Development 101 SlidesSlack Application Development 101 Slides
Slack Application Development 101 Slidespraypatel2
 
08448380779 Call Girls In Friends Colony Women Seeking Men
08448380779 Call Girls In Friends Colony Women Seeking Men08448380779 Call Girls In Friends Colony Women Seeking Men
08448380779 Call Girls In Friends Colony Women Seeking MenDelhi Call girls
 
Developing An App To Navigate The Roads of Brazil
Developing An App To Navigate The Roads of BrazilDeveloping An App To Navigate The Roads of Brazil
Developing An App To Navigate The Roads of BrazilV3cube
 
CNv6 Instructor Chapter 6 Quality of Service
CNv6 Instructor Chapter 6 Quality of ServiceCNv6 Instructor Chapter 6 Quality of Service
CNv6 Instructor Chapter 6 Quality of Servicegiselly40
 
Presentation on how to chat with PDF using ChatGPT code interpreter
Presentation on how to chat with PDF using ChatGPT code interpreterPresentation on how to chat with PDF using ChatGPT code interpreter
Presentation on how to chat with PDF using ChatGPT code interpreternaman860154
 
Factors to Consider When Choosing Accounts Payable Services Providers.pptx
Factors to Consider When Choosing Accounts Payable Services Providers.pptxFactors to Consider When Choosing Accounts Payable Services Providers.pptx
Factors to Consider When Choosing Accounts Payable Services Providers.pptxKatpro Technologies
 
🐬 The future of MySQL is Postgres 🐘
🐬 The future of MySQL is Postgres 🐘🐬 The future of MySQL is Postgres 🐘
🐬 The future of MySQL is Postgres 🐘RTylerCroy
 
The Role of Taxonomy and Ontology in Semantic Layers - Heather Hedden.pdf
The Role of Taxonomy and Ontology in Semantic Layers - Heather Hedden.pdfThe Role of Taxonomy and Ontology in Semantic Layers - Heather Hedden.pdf
The Role of Taxonomy and Ontology in Semantic Layers - Heather Hedden.pdfEnterprise Knowledge
 

Dernier (20)

Exploring the Future Potential of AI-Enabled Smartphone Processors
Exploring the Future Potential of AI-Enabled Smartphone ProcessorsExploring the Future Potential of AI-Enabled Smartphone Processors
Exploring the Future Potential of AI-Enabled Smartphone Processors
 
08448380779 Call Girls In Civil Lines Women Seeking Men
08448380779 Call Girls In Civil Lines Women Seeking Men08448380779 Call Girls In Civil Lines Women Seeking Men
08448380779 Call Girls In Civil Lines Women Seeking Men
 
Top 5 Benefits OF Using Muvi Live Paywall For Live Streams
Top 5 Benefits OF Using Muvi Live Paywall For Live StreamsTop 5 Benefits OF Using Muvi Live Paywall For Live Streams
Top 5 Benefits OF Using Muvi Live Paywall For Live Streams
 
How to convert PDF to text with Nanonets
How to convert PDF to text with NanonetsHow to convert PDF to text with Nanonets
How to convert PDF to text with Nanonets
 
Neo4j - How KGs are shaping the future of Generative AI at AWS Summit London ...
Neo4j - How KGs are shaping the future of Generative AI at AWS Summit London ...Neo4j - How KGs are shaping the future of Generative AI at AWS Summit London ...
Neo4j - How KGs are shaping the future of Generative AI at AWS Summit London ...
 
2024: Domino Containers - The Next Step. News from the Domino Container commu...
2024: Domino Containers - The Next Step. News from the Domino Container commu...2024: Domino Containers - The Next Step. News from the Domino Container commu...
2024: Domino Containers - The Next Step. News from the Domino Container commu...
 
Driving Behavioral Change for Information Management through Data-Driven Gree...
Driving Behavioral Change for Information Management through Data-Driven Gree...Driving Behavioral Change for Information Management through Data-Driven Gree...
Driving Behavioral Change for Information Management through Data-Driven Gree...
 
04-2024-HHUG-Sales-and-Marketing-Alignment.pptx
04-2024-HHUG-Sales-and-Marketing-Alignment.pptx04-2024-HHUG-Sales-and-Marketing-Alignment.pptx
04-2024-HHUG-Sales-and-Marketing-Alignment.pptx
 
Apidays Singapore 2024 - Building Digital Trust in a Digital Economy by Veron...
Apidays Singapore 2024 - Building Digital Trust in a Digital Economy by Veron...Apidays Singapore 2024 - Building Digital Trust in a Digital Economy by Veron...
Apidays Singapore 2024 - Building Digital Trust in a Digital Economy by Veron...
 
Automating Google Workspace (GWS) & more with Apps Script
Automating Google Workspace (GWS) & more with Apps ScriptAutomating Google Workspace (GWS) & more with Apps Script
Automating Google Workspace (GWS) & more with Apps Script
 
Histor y of HAM Radio presentation slide
Histor y of HAM Radio presentation slideHistor y of HAM Radio presentation slide
Histor y of HAM Radio presentation slide
 
[2024]Digital Global Overview Report 2024 Meltwater.pdf
[2024]Digital Global Overview Report 2024 Meltwater.pdf[2024]Digital Global Overview Report 2024 Meltwater.pdf
[2024]Digital Global Overview Report 2024 Meltwater.pdf
 
Slack Application Development 101 Slides
Slack Application Development 101 SlidesSlack Application Development 101 Slides
Slack Application Development 101 Slides
 
08448380779 Call Girls In Friends Colony Women Seeking Men
08448380779 Call Girls In Friends Colony Women Seeking Men08448380779 Call Girls In Friends Colony Women Seeking Men
08448380779 Call Girls In Friends Colony Women Seeking Men
 
Developing An App To Navigate The Roads of Brazil
Developing An App To Navigate The Roads of BrazilDeveloping An App To Navigate The Roads of Brazil
Developing An App To Navigate The Roads of Brazil
 
CNv6 Instructor Chapter 6 Quality of Service
CNv6 Instructor Chapter 6 Quality of ServiceCNv6 Instructor Chapter 6 Quality of Service
CNv6 Instructor Chapter 6 Quality of Service
 
Presentation on how to chat with PDF using ChatGPT code interpreter
Presentation on how to chat with PDF using ChatGPT code interpreterPresentation on how to chat with PDF using ChatGPT code interpreter
Presentation on how to chat with PDF using ChatGPT code interpreter
 
Factors to Consider When Choosing Accounts Payable Services Providers.pptx
Factors to Consider When Choosing Accounts Payable Services Providers.pptxFactors to Consider When Choosing Accounts Payable Services Providers.pptx
Factors to Consider When Choosing Accounts Payable Services Providers.pptx
 
🐬 The future of MySQL is Postgres 🐘
🐬 The future of MySQL is Postgres 🐘🐬 The future of MySQL is Postgres 🐘
🐬 The future of MySQL is Postgres 🐘
 
The Role of Taxonomy and Ontology in Semantic Layers - Heather Hedden.pdf
The Role of Taxonomy and Ontology in Semantic Layers - Heather Hedden.pdfThe Role of Taxonomy and Ontology in Semantic Layers - Heather Hedden.pdf
The Role of Taxonomy and Ontology in Semantic Layers - Heather Hedden.pdf
 

Intel Xeon Pre-Silicon Validation: Introduction and Challenges

  • 1. Intel Xeon Pre-Silicon Validation Introduction & Challenges Paul Zehr December 5, 2006
  • 2. 2 Agenda This talk is intended to be an intro to Xeon pre- silicon validation work & challenges: Please stop me & ask questions Introduction • What is a “typical” Xeon processor Challenges • Re-Use • Some managerial issues • The usual…
  • 3. 3 What is a Xeon Processor? Silicon Processor Core Processor Cores Processor Cores Cache… Power-related New Technologies… Can be anything from a simple cache size increase to full blown from-scratch development of features RAS
  • 4. 4 Parameters Driving Xeon Validation TTM is the key driving factor • Quick ramp time new features need comprehending quickly Relatively “small” teams Validation “dominates” wrt team size • Bonus: high demand for talented DV engineers Focus is on what’s new & changed • Still need to validate full chip • Beware: minor design changes can have broad impact Heavy re-use of other design environments • Combining environments always sounds easier at proj. conception… Tend to be cross-site efforts Trend: More & more from-scratch design being added
  • 5. 5 Challenges: Re-Use First, a few examples: • Merced’s bus cluster • Whitefield Expectation is that gluing various pieces of design together is fast & easy • State of the “parent” design can be an issue… Varying design languages / environments A lot of code implemented for “single use” • Poorly written code from parent projects • Never intended to be proliferated in the first place Engineers need to understand original intent Re-use of unfinished code
  • 6. 6 Challenges: Managerial Influence of validation on project design during concept phase • Stop feature creep at the source… • “simple” arch deltas can cause inordinate validation Cross-site teams Documentation & training from parent project(s) Retention • Need experienced teams to meet goals, but, • Also need development challenges to retain…
  • 7. 7 Challenges: The Usual Model Size & Speed • Emulation & Formal help, but… • Speed exacerbated by ever-growing number of clock domains • Ever-increasing sets of tools doesn’t help either Emulation: • Long initial RTL model build time (months). • Less granular checking • Debug requires extra steps • Not a real effective way to get out early bugs. Formal for specific areas, but isn’t mature • Meaning: We still simulate everything
  • 8. 8 Challenges (cont.) Stimulus: We tend to be very repetitive: • “Start-Up” code is almost identical for 1000’s of tests • RIT example: S/W semaphores (or barriers) & interrupt handlers – Many RIT generators code “macros” – same code each time – Some people have gotten creative here, but needs more • Challenge is to minimize duplicate code – especially in the large bug-hunting runs. Checking: Escapes rarely due to lack of checking • Checker overhead still an issue – Code ‘em into RTL – helps emulation as well – Could aid in post-Si debug if done properly Coverage: Again, adds overhead to the model • A lot of philosophical differences here – internally & externally… • Need better solutions with less overhead – See checking. Debug: Vendors need to understand varying needs • Large, monolithic all-in-one solutions don’t suit all
  • 9. 9 A bit more on stimulus & coverage Low % Covered ~100 % Covered
  • 10. 10 Challenges (cont.) Cross over between pre & post Si • Portability of tests between post & pre silicon – Implications on environment • Circuits/phys. design & implementation need functional tests to find timing & noise – Intent verification requires ability to run on pre-si models