Join Matthew Harms as he discusses a unique multi-tiered strategy to board analysis & verification designed to enable designers of all skill levels to analyze their PCB designs early in the development cycle when the cost of change is the lowest. Matthew will show how Cadence has created a multi-tier analysis environment that lets designers start with a set of pre-defined Electrical Rule Checks (ERC) that can be run on the board to quickly identify areas of interest or concern all without the need for any complex models or configurations. Based on these initial 1st order results Matthew will show how design teams can then effectively target critical nets with 2nd order (Simulation Rule Checks) and 3rd order (Power Aware Signal Integrity) analysis as needed to simulate with greater detail and achieve complete electrical design signoff.

1. OrCAD Now! Anaheim
Signal Integrity Presentation
Matthew Harms
Field Applications Engineer
matthewh@ema-eda.com

2. Advanced layout check
Coupling overlay in layout
Coupling plot
Coupling table
ERC
Electrical rule check
SRC
Simulation rule check

3. •SI metrics check is a simulation-based PCB check
•It can be done at 3 levels, based on considerations of trace/via couplings and non-ideal PDN effects
Three levels of SI/PI simulations
SI/ PIsimulation level
Trace coupling
Via coupling
Power-aware
(non-ideal PDN)
SI/PI effects captured
Level 1
No
Within pairtrace coupling for diff pairs included
No
Withinpair via coupling for diff pairs included
No
Delay;
Reflection;
Loss
Level 2
Yes
Yes
No
Crosstalk
Level 3
Yes
Yes
Yes
Returnpath discontinuity;
SSO

4. Electrical Rule Check (ERC)

5. ERC –Electric rule check
•ERC is a power-aware PCB check in geometry domain for
–Electrical length
–Trace impedance
–Trace coupling
–Trace upper/lower layer, and coplanar references, or the lack thereof
–Differential routing in phase, or out of phase
–Via coupling
August 19, 2014 •© 2014 Cadence Design Systems, 5 Inc. All rights reserved.

6. Two trace segments exampleDRC –Simplified view
•2 trace segments, same trace width, same impedance
trace9048
August 19, 2014 •© 2014 Cadence Design Systems, 6 Inc. All rights reserved.

7. Two trace segments example
•DDR3 SODIMM
•2 trace segments for net DQ0 on layer3
trace9047
trace9048
Zoom in on 2 trace segments on Layer3
August 19, 2014 •© 2014 Cadence Design Systems, 7 Inc. All rights reserved.

8. Two trace segments exampleIf you look close enough…
•Trace9047: one uniform impedance section
•Trace9048: 4 impedance sections
trace9048
Signal layer + plane layers directly above and below
August 19, 2014 •© 2014 Cadence Design Systems, 8 Inc. All rights reserved.

9. Two trace segments exampleERC –Impedance
•ERC results also shows trace9047 has one impedance section
•But trace9048 actually has 5impedance sections when all layers are considered
1
2
3
4
5
August 19, 2014 •© 2014 Cadence Design Systems, 9 Inc. All rights reserved.

10. Two trace segments exampleERC –Trace coupling
•Trace9047 broken into 5 sections based on trace coupling
1
2
3
4
5
1
2
3
4
5
August 19, 2014 •© 2014 Cadence Design Systems, 10 Inc. All rights reserved.

11. Two trace segments exampleERC –Trace upper/lower layer reference
•Based on upper/lower layer references
–Trace9047 one section
–Trace9048 5 sections
trace9048
August 19, 2014 •© 2014 Cadence Design Systems, 11 Inc. All rights reserved.

12. Two trace segments exampleERC –Trace coplanar reference
•Both trace do not have coplanar reference shapes
trace9048
August 19, 2014 •© 2014 Cadence Design Systems, 12 Inc. All rights reserved.

13. Two trace segments example
From 2 trace segments to entire board
Oh, no!
• If ERC results are useful, can you image doing that for the
entire PCB?
• At larger scale, you will need ERC to help you
August 19, 2014 •© 2014 Cadence Design Systems, 13 Inc. All rights reserved.

14. Whole board ERC does not get any easier

15. 1.Load spd file
2.Select option ‘Check all nets’
3.Run simulation
(cont.)
1
2
3
As easy as

16. Results in 6 tables

17. ERC with NetGroups

18. Impedance/Coupling Plot
Collapsed
18

19. Impedance/Coupling Plot
Expanded
19

20. Simulation Rule Check (SRC)

21. 1.Comprehensive and practical for board level electrical design check
2.Easy and fast setup
–Simple Tx voltage stimulus and Rx termination models
–Net groups are automatically generated for different interfaces
3.Simulation levels: level1 to level3
4.Results automatically post processed
–Rx/Tx/FEXT/NEXT waveform results
–SI performance metrics (using Rx and FEXT waveforms)
–Check report (files, setup, and results)
Simulation Rule Check Overview
Example:
•1 CPU
•4 memory channels,
•8 DIMM
•420 nets
•Setup time 3 min with 8 automatically generated net groups

22. •A DDR design is used in this tutorial
–Controller U0, 4 DRAMs U1-U4
Board for tutorial

23. SRC –Simulation Rule CheckTime-domain waveforms
•The ckt and waveforms and ckt
Rx/Tx/FEXT/NEXTwaveforms
August 19, 2014 •© 2014 Cadence Design Systems, 23 Inc. All rights reserved.

24. • Waveforms
Rx waveform
FEXT waveform
     
Int ISI  Int xtk 
Int sig
SN ratio
SN difference Int sig Int ISI Int xtk
Int xtk fext t dt
Int ISI Rx t dt Rx t dt
Int sig Rx t dt
t
i
t
t
t
t
t
_ _
_
_
_ _ _ _
_ ( )
_ ( ) ( )
_ ( )
max
max
2
1
2
1
0
0


  

 


 





( ) ( )
( ) ( )
NEXT t next t
FEXT t fext t
i
i
• SI metrics are defined using magnitudes
of Rx and FEXT
SRC – Simulation rule check
SI metrics
24 August 19, 2014 ©• 2014 Cadence Design Systems, Inc. All rights reserved.

25. SRC –Simulation rule checkNet-level performance ranking
Ranking by SI Metrics
Ranking by xtalk levels
August 19, 2014 •© 2014 Cadence Design Systems, 25 Inc. All rights reserved.

26. General SI Workflow

27. General SI Simulation(GSI) workflow is a newly introduced general purpose Level-1 and Level-2 SI analysis workflow
•Layout based
•Ideal power/ground
•Easy to set up
•Fast simulation
ASI16.63 new: GeneralSI Simulation workflow

28. How GSI workflow works

29. •Enable all nets except power net VTT_REF
•Check diff pairs and polarities
Step 1: Select Nets

30. •Assign power nets voltage
•Voltages for gnd nets are assumed to be 0v
Step 2: Assign power net voltage

31. •About a component and its models
–Component name (from layout file)
–Component part name (from layout file)
–Component types (auto assigned, user can re-assign it)
–Component models (user assigned)
Step 3: Assign component models

32. Step 4: Set up SI simulation options

33. •Un-select waveform at driver pins (all pins for U0)
•Leave all receiver pins at DRAMs selected
Step 5: Set up probes

34. •Check ‘Shape Processing’ if shown
–If not shown, the shapes have been processed and saved
•Check ‘Error Checking’
Step 6: Save

35. •Layout and simulation setup is loaded to simulator spdsim
•After trace/pad parameters extraction, simulation will start one net/pair at a time
–A differential pair is handled in one simulation
Step 7 Running Simulations

36. •Both pin and pad waveforms are available
Step 8: View results

37. Simulation considering non-ideal PDN

38. •SI metrics check is a simulation-based PCB check
•It can be done at 3 levels, based on considerations of trace/via couplings and non-ideal PDN effects
Three levels of SI/PI simulations
SI/ PIsimulation level
Trace coupling
Via coupling
Power-aware
(non-ideal PDN)
SI/PI effects captured
Level 1
No
Within pairtrace coupling for diff pairs included
No
Withinpair via coupling for diff pairs included
No
Delay;
Reflection;
Loss
Level 2
Yes
Yes
No
Crosstalk
Level 3
Yes
Yes
Yes
Returnpath discontinuity;
SSO

39. •Large signal degradation due to non-ideal PDN effect
•Level-2 simulation failed to show it
AddCmd results @U103
Level-1
Level-3
Level-2

40. Power Integrity Analysis

41. current density with temperature awareness
temperature due to Joule (copper) and component heating
PowerDC
•Electrical resistance increases at higher temperatures
•Component leakage power dissipation increases at higher temperatures
Iterate
until
converged
Thermal Simulation
temperature
Electrical Simulation
current density
•Copper (Joule) heating will affect temperature distributions
PowerDC
Integrated Electrical & Thermal Co-Simulation
41

42. Electrical Results
42

43. •OptimizePI is a highly automated board AC frequency analysis solution
•Supports pre and post-layout decapstudies and identifies impedance issues
•Decapimplementations are optimized for performance and cost.
OptimizePI
Overview

44. Original Design
Scheme29 (15cents saving)
78mV
68mV
12% noise improved
21% cost saving
Correlation to Time Domain
Better performance at less cost
44

45. •PowerSI is an advanced signal integrity, power integrity and design-stage EMI solution
•Supports S- parameter model extraction and provides robust frequency domain simulation for entire PCB design
PowerSI
Overview
45

46. •Identify impedance “hot spots”
•Place decoupling capacitors in areas exceeding target impedance
•Analyze power / ground resonance
•Minimize component costs with optimized decoupling
PowerSI
Analyze Decoupling Capacitor Selection and Placement
46