3. Shift Registers
• Flip flops can be used to store a single bit of binary
data (1or 0).
• However, in order to store multiple bits of data, we
need multiple flip flops.
• N flip flops are to be connected in an order to store
n bits of data.
• A Register is a device which is used to store such
information. It is a group of flip flops connected in
series used to store multiple bits of data.
4. Contd..
• The information stored within these registers can be
transferred with the help of shift registers.
• An n-bit shift register can be formed by connecting n
flip-flops where each flip flop stores a single bit of data.
• The registers which will shift the bits to left are called
“Shift left registers”. (Makes multiplication by 2)
The registers which will shift the bits to right are called
“Shift right registers”. (Makes division by 2)
• Shift registers are basically of 4 types. These are:
• Serial In Serial Out shift register
• Serial In parallel Out shift register
• Parallel In Serial Out shift register
• Parallel In parallel Out shift register
5. Serial-In Serial-Out Shift Register
(SISO) –
• The shift register, which allows serial input (one bit after the
other through a single data line) and produces a serial
output is known as Serial-In Serial-Out shift register.
• Since there is only one output, the data leaves the shift
register one bit at a time in a serial pattern, thus the name
Serial-In Serial-Out Shift Register.
• The circuit consists of four D flip-flops which are connected
in a serial manner. All these flip-flops are synchronous with
each other since the same clock signal is applied to each flip
flop.
6. • The above circuit is an example of shift right
register, taking the serial data input from the left
side of the flip flop.
• The main use of a SISO is to act as a delay element.
• Initially value is 0000
• Taking value of Q3Q2Q1Q0 = 1010
• Then following table works:
Clock
Signals
Q3 Q2 Q1 Q0
Initially 0 0 0 0
CLK-1 0 0 0 0
CLK-2 1 0 0 0
CLK-3 0 1 0 0
CLK-4 1 0 1 0
7. • So we can say, in n- bit register we need n clock
pulses to LOAD the value.
• To Read the clock pulse = (n-1)
8. Serial-In Parallel-Out shift Register
(SIPO) –
• The shift register, which allows serial input (one bit after the other
through a single data line) and produces a parallel output is known as
Serial-In Parallel-Out shift register.
• The logic circuit given below shows a serial-in-parallel-out shift register.
The circuit consists of four D flip-flops which are connected. The clear
(CLR) signal is connected in addition to the clock signal to all the 4 flip
flops in order to RESET them.
• The output of the first flip flop is connected to the input of the next flip
flop and so on. All these flip-flops are synchronous with each other since
the same clock signal is applied to each flip flop.
9. • The above circuit is an example of shift right
register, taking the serial data input from the left
side of the flip flop and producing a parallel output.
• They are used in communication lines where
demultiplexing of a data line into several parallel
lines is required because the main use of the SIPO
register is to convert serial data into parallel data.
• Here for loading you will be needing ‘n’ clock pulse
only for n-bit register
• But for reading, the output is parallel means its
ready at that time, so time taken=0.
10. Parallel-In Serial-Out Shift Register
(PISO) –
• The shift register, which allows parallel input (data is given
separately to each flip flop and in a simultaneous manner) and
produces a serial output is known as Parallel-In Serial-Out shift
register.
• The logic circuit given below shows a parallel-in-serial-out shift
register.
• The circuit consists of four D flip-flops which are connected.
• The clock input is directly connected to all the flip flops but the
input data is connected individually to each flip flop through a
multiplexer at the input of every flip flop.
• The output of the previous flip flop and parallel data input are
connected to the input of the MUX and the output of MUX is
connected to the next flip flop.
• All these flip-flops are synchronous with each other since the
same clock signal is applied to each flip flop.
11. • A Parallel in Serial out (PISO) shift register used to
convert parallel data to serial data.
12. • In this, for loading only in 1 clock pulse all n-bits
will be loaded.
• For reading = (n-1)
13. Parallel-In Parallel-Out Shift
Register (PIPO) –
• The shift register, which allows parallel input (data is given
separately to each flip flop and in a simultaneous manner) and
also produces a parallel output is known as Parallel-In parallel-Out
shift register.
• The logic circuit given below shows a parallel-in-parallel-out shift
register.
• The circuit consists of four D flip-flops which are connected.
• The clear (CLR) signal and clock signals are connected to all the 4
flip flops.
• In this type of register, there are no interconnections between the
individual flip-flops since no serial shifting of the data is required.
• Data is given as input separately for each flip flop and in the same
way, output also collected individually from each flip flop.
14. • A Parallel in Parallel out (PIPO) shift register is used
as a temporary storage device and like SISO Shift
register it acts as a delay element.
• Here for loading we need 1 clock pulse.
• For reading we need 0 clock pulse
15. Mode Clocks needed for n-bit shift register
Loading Reading Total
SISO n n-1 2n-1
SIPO n 0 n
PISO 1 n-1 n
PIPO 1 0 1
16. Bidirectional Shift Register –
• If we shift a binary number to the left by one position, it is equivalent to
multiplying the number by 2 and if we shift a binary number to the right
by one position, it is equivalent to dividing the number by 2.
• To perform these operations we need a register which can shift the data
in either direction.
• Bidirectional shift registers are the registers which are capable of
shifting the data either right or left depending on the mode selected.
• If the mode selected is 1(high), the data will be shifted towards the right
direction and if the mode selected is 0(low), the data will be shifted
towards the left direction.
• The logic circuit given below shows a Bidirectional shift register. The
circuit consists of four D flip-flops which are connected.
• The input data is connected at two ends of the circuit and depending on
the mode selected only one and gate is in the active state.
17.
18. Counters
• A special type of sequential circuit used to count the
pulse is known as a counter, or a collection of flip flops
where the clock signal is applied is known as counters.
• The counter is one of the widest applications of the flip
flop. Based on the clock pulse, the output of the
counter contains a predefined state. The number of the
pulse can be counted using the output of the counter
• There are the following types of counters:
• Asynchronous Counters
• Synchronous Counters
19. Asynchronous Counters
• In asynchronous counter
we don’t use universal
clock, only first flip flop is
driven by main clock and
the clock input of rest of
the following flip flop is
driven by output of
previous flip flops.
• We can understand it by
following diagram-
20. Contd..
• It is evident from timing diagram that Q0 is
changing as soon as the rising edge of clock pulse
is encountered, Q1 is changing when rising edge
of Q0 is encountered(because Q0 is like clock
pulse for second flip flop) and so on.
• In this way ripples are generated through
Q0,Q1,Q2,Q3 hence it is also
called RIPPLE counter. A ripple counter is a
cascaded arrangement of flip flops where the
output of one flip flop drives the clock input of the
following flip flop .
•
21. Synchronous Counter
• Unlike the asynchronous
counter, synchronous
counter has one global
clock which drives each flip
flop so output changes in
parallel.
• The one advantage of
synchronous counter over
asynchronous counter is, it
can operate on higher
frequency than
asynchronous counter as it
does not have cumulative
delay because of same
clock is given to each flip
flop.
22. • Synchronous counter circuit
Timing diagram
synchronous counter
From circuit diagram we see
that Q0 bit gives response to
each falling edge of clock while
Q1 is dependent on Q0, Q2 is
dependent on Q1 and Q0 , Q3
is dependent on Q2,Q1 and
Q0.
23. Ripple Counter
• Ripple counter is a special type of Asynchronous counter in which the
clock pulse ripples through the circuit.
• The n-MOD ripple counter forms by combining n number of flip-flops. The
n-MOD ripple counter can count 2n states, and then the counter resets to
its initial value.
• Features of the Ripple Counter:
• Different types of flip flops with different clock pulse are used.
• It is an example of an asynchronous counter.
• The flip flops are used in toggle mode.
• The external clock pulse is applied to only one flip flop. The output of this flip flop is
treated as a clock pulse for the next flip flop.
• In counting sequence, the flip flop in which external clock pulse is passed, act as
LSB.
• A counter may be an up counter that counts upwards or can be a down counter
that counts downwards or can do both i.e. count up as well as count downwards
depending on the input control. The sequence of counting usually gets repeated
after a limit. When counting up, for the n-bit counter the count sequence goes
from 000, 001, 010, … 110, 111, 000, 001, … etc. When counting down the count
sequence goes in the opposite manner: 111, 110, … 010, 001, 000, 111, 110, …
etc.
24. • Below is a diagram of the 2-bit Asynchronous
counter in which we used two T flip-flops.
Apart from the T flip flop, we can also use
the JK flip flop by setting both of the inputs to 1
permanently.
• The external clock pass to the clock input of
the first flip flop, i.e., FF-A and its output, i.e., is
passed to clock input of the next flip flop, i.e.,
FF-B.
• Block Diagram
26. • A 3-bit Ripple counter using a JK flip-flop is as follows:
• In the circuit shown in the above figure, Q0(LSB) will
toggle for every clock pulse because JK flip-flop works
in toggle mode when both J and K are applied 1, 1, or
high input. The following counter will toggle when the
previous one changes from 1 to 0.
27. • Let us assume that the clock is negative edge
triggered so the above the counter will act as an up
counter because the clock is negative edge
triggered and output is taken from Q.
28. Modulus Counter (MOD-N
Counter)
• It is a number of the states that the counter passes
through before reaching to its original value.
• Examples:
• 2 bit counter (Mod-4 Counter)
• 3 bit counter (Mod-8 counter)
• 4 bit counter (Mod-16 counter)
• Sometimes counter truncates in between the states
and some of the states are not used.
• Example
• MOD-5
• MOD-6
• MOD-10
29. Mod – N synchronous Counter
• The following method is applied for designing for mod N and
any counting sequence.
• Design for Mod-N counter :
The steps for the design are –
• Step 1 : Decision for number of flip-flops –
• Example : If we are designing mod N counter and n number of
flip-flops are required then n can be found out by this equation.
• N <= 2n
• Here we are designing Mod-10 counter Therefore, N= 10 and
number of Flip flops(n) required is
• For n =3, 10<=8, which is false.
• For n= 4,10<=16, which is true.
• Therefore, number of FF required is 4 for Mod-10 counter.
30. • Step 2 : Write excitation table of Flip flops –
Here T FF is used
• Step 3 : Draw state diagram and circuit
excitation table –
31. • A decade counter is called as mod -10 or divide by 10
counter. It counts from 0 to 9 and again reset to 0. It
counts in natural binary sequence. Here 4 T Flip flops
are used. It resets after Q3 Q2 Q1 Q0 = 1001.
• Circuit excitation table –
Here Q3 Q2 Q1 Q0 are present states of four flip-flops
and Q*3 Q*2 Q*1 Q*0 are next counting state of 4 Flip
flops. If there is a transition in current state i.e if Q3
value changes from 0 to 1 or 1 to 0 then there’s
corresponding T(toggle) bit is written as 1 otherwise 0.
32. • Step 4 : Create Karnaugh map for each FF
input in terms of flip-flop outputs as the
input variable –
Simplify the K map –
33. • Step 5 : Create circuit diagram –
Here negative edge triggered clock is used for
toggling purpose.
• The clock is provided to every Flip flop at same
instant of time.
• The toggle(T) input is provided to every Flip
flop according to the simplified equation of K
map.
•
34. Ring Counter
• A ring counter is a typical application of the
Shift register. The ring counter is almost the
same as the shift counter.
• The only change is that the output of the last
flip-flop is connected to the input of the first flip-
flop in the case of the ring counter but in the
case of the shift register it is taken as output.
• Except for this, all the other things are the
same.
• No of states in Ring Counter = No. of flip flop
used
35. • So, for designing a 4-bit Ring counter we need 4 flip-flops.
• In this diagram, we can see that the clock pulse (CLK) is
applied to all the flip-flops simultaneously. Therefore, it is a
Synchronous Counter. Also, here we use Overriding input
(ORI) for each flip-flop. Preset (PR) and Clear (CLR) are
used as ORI. When PR is 0, then the output is 1. And when
CLR is 0, then the output is 0. Both PR and CLR are active
low signal that always works in value 0.
• PR = 0, Q = 1
• CLR = 0, Q = 0
36. • These two values are always fixed. They are
independent of the value of input D and the
Clock pulse (CLK).
• Working – Here, ORI is connected to Preset
(PR) in FF-0 and it is connected to Clear (CLR)
in FF-1, FF-2, and FF-3. Thus, output Q = 1 is
generated at FF-0, and the rest of the flip-flop
generates output Q = 0. This output Q = 1 at
FF-0 is known as Pre-set 1 which is used to
form the ring in the Ring Counter.
37. • This Preseted 1 is generated by making ORI low and that time
Clock (CLK) becomes don’t care.
• After that ORI is made to high and apply low clock pulse signal as
the Clock (CLK) is negative edge triggered.
• After that, at each clock pulse, the preseted 1 is shifted to the next
flip-flop and thus forms a Ring. From the above table, we can say
that there are 4 states in a 4-bit Ring Counter.
• 4 states are:
• 1 0 0 0
• 0 1 0 0
• 0 0 1 0
• 0 0 0 1
• In this way can design a 4-bit Ring Counter using four D flip-flops.
• Types of Ring Counter: There are two types of Ring Counter:
• Straight Ring Counter
• Twisted Ring Counter
38. • Straight Ring Counter:
• It is also known as One hot Counter. In this
counter, the output of the last flip-flop is
connected to the input of the first flip-flop.
The main point of this Counter is that it
circulates a single one (or zero) bit around
the ring.
• Here, we use Preset (PR) in the first flip-flop
and Clock (CLK) for the last three flip-flops.
39. • Total no. of states in n-bit Ring counter=n.
• Therefore, we can say Mod n counter
• How many are usable states?
• Taking an example of 4 bit ring counter.
• Total no. of states = n = 4.
• Although, possible no.of states = 2^n = 2^4 = 16
• So, usable states = 4
• Unused states = 16-4 = 12 states
40. • Twisted Ring Counter
• It is also known as a switch-tail ring counter,
walking ring counter, or Johnson counter.
• It connects the complement of the output of the
last shift register to the input of the first register
and circulates a stream of ones followed by zeros
around the ring.
• Here, we use Clock (CLK) for all the flip-flops. In
the Twisted Ring Counter, the number of states = 2
X the number of flip-flops.
41. • Here take Q0Q1Q2Q3 = 0000
• In twisted ring Q3’ is connected to D0.
• Therefore 0000 state will work.
• Q0(n+1) = D0= Q3’
• Possible states are = 8
• Different states here :
• if n – bit = 2n
• Used states = 2n
Q0 Q1 Q2 Q3
0 0 0 0
1 0 0 0
1 1 0 0
1 1 1 0
1 1 1 1
0 1 1 1
0 0 1 1
0 0 0 1
0 0 0 0
