2. Table of Contents
Answer of Q-1........................................................................................................................... 3
Answer of Q -2.......................................................................................................................... 5
Answer of Q -3.......................................................................................................................... 7
Answer of Q -4.......................................................................................................................... 9
Answer of Q -5........................................................................................................................ 10
Answer of Q -6........................................................................................................................ 10
Answer of Q -7........................................................................................................................ 12
Answer of Q -8........................................................................................................................ 12
References.............................................................................................................................. 14
3. Answer of Q-1
As directed in the instruction, the binary data 110101 will be converted to the
corresponding Analog signal by using the modulation technique. Those outcomes are
shown below serially to demonstrate the answer (Hai Xue, 2018).
a) 2-Level ASK outcome is as below:
b) 2-Level FSK outcome is as below:
c) 2-Level PSK outcome is as below:
4. d) DPSK outcome is as below:
e) 4-Level ASK outcome is as below:
f) 4-Level PSK outcome is as below:
5. g) 8-Level ASK outcome is as below:
Answer of Q -2
In this section, the frequency assignment will be computed and thereby assign the
frequency to the respective component of the frequency, using the MFSK modulation
and with help of the given parameters as follows (D. Kreutz, 2015):
fc= 1000 KHz Carrier Frequency
fd = 50 KHz Difference Frequency
M = 16 Signal Level
L = log2(M) = log2(16) = 4 Number of bits in each component
So, to check the frequency assignment, primarily, the frequency components or levels
are shown as follows:
6. Component-0 is binary 0000
Component-1 is binary 0001
Component-2 is binary 0010
Component-3 is binary 0011
Component-4 is binary 0100
Component-5 is binary 0101
Component-6 is binary 0110
Component-7 is binary 0111
Component-8 is binary 1000
Component-9 is binary 1001
Component-10 is binary 1010
Component-11 is binary 1011
Component-12 is binary 1100
Component-13 is binary 1101
Component-14 is binary 1110
Component-15 is binary 1111
Now, the assigned frequency for each of the components can be calculated as follows
which is based on the parameters shown earlier (B. A. A. Nunes, 2014):
fi=fc+(2×i-1-M)×fd
With help of the formula shown above, the assigned frequency for the mentioned
components are as follows:
Component 0000 0001 0010 0011
Frequency 250 KHz 350 KHz 450 KHz 550 KHz
Component 0100 0101 0110 0111
Frequency 650 KHz 750 KHz 850 KHz 950 KHz
Component 1000 1001 1010 1011
Frequency 1050 KHz 1150 KHz 1250 KHz 1350 KHz
Component 1100 1101 1110 1111
Frequency 1450 KHz 1550 KHz 1650 KHz 1750 KHz
7. Answer of Q -3
The Frequency and Analog modulation will be shown in this section on behalf of the
input signal that is given in the question. The input signal is shown below.
The input signal has the parameters like the amplitude is of 0.5 volt along with the
frequency of 0.016 Hertz as the time period is about 1 minute or 60 seconds and so
frequency will be the inverse of the time period.
Below the steps of the Analog modulation and Frequency modulations are described
with graphical representation of the signals and other required elements (Woensel,
2014).
Steps for Analog Modulation:
The steps for the conversion of the Analog modulation is shown below:
i. Carrier signal is the primary important part of the modulation and hence is
taken as the input.
ii. The second input fact is to take input of the message signal that is provided
in the instruction and upon which the modulation will be done is as follows:
8. iii. These two input signal will be provided into the Analog Modulator which will
modulate the message signal in accordance with the carrier signal. The
structure of the modulator is shown below:
iv. Finally, the modulator will provide the modulated signal using the Analog
Modulation process.
The Analog modulated signal is shown above with the process above.
Steps for Frequency Modulation:
The steps for the conversion of the Frequency modulation is shown below (Pandya,
2017):
i. Carrier signal is the primary important part of the modulation and hence is
taken as the input.
ii. The second input fact is to take input of the message signal that is provided
in the instruction and upon which the modulation will be done is as follows:
9. iii. These two inputs signal will be provided into the Fequency Modulator which
will modulate the message signal in accordance with the carrier signal. The
structure of the modulator is shown below:
iv. Finally, the modulator will provide the modulated signal using the Frequency
Modulation process.
The Frequency modulated signal is shown above with the process above.
Answer of Q -4
Modulation is the process which converts one signal type to another. There are
different modulation processes are there which convert one other. Quadrature
Amplitude Modulation is the process of modulation. Every modulation process
contains error but most of the time the error cannot be identified properly (Hai Xue,
2018). This error in the modulation is found by the constellation diagram. In this
problem, the constellation diagram is shown for the QAM with 16 phase that is for
QAM-16 with 4 different phases and 4 different amplitude level. The required
constellation diagram is shown below:
In this figure, the constellation diagram is shown for 16-QAM with different phase and
amplitude as desired.
10. Answer of Q -5
Cyclic Redundancy Check is the process to check the error in the transmitted data in
a media or storage. Generally, the data is transferred from one point to another or
more specifically, from transmitter or end of sender to the receiver. This data will be
check at both two points for the consistence that is to check whether the transmitted
data and the received data are same. If the data is same, then this will be received
and if not, that will be rejected for having error. The checking is done using the division
process. At the sender end, the division is done and the check bit r the CRC bit is
appended with the data bit stream. This data again will be checked at the receiving
end and check for the remainder. If the remainder bit or the check bit at two sides are
same, then the data is considered as error free and thus will be accepted and the data
will be rejected is the remainder bit is not same (Woensel, 2014).
The process of the Cyclic Redundancy Check is shown below:
The process from for the CRC checker and the generator is shown above. This
process will check for ten consistency of the data and determines for the correctness
of the data while receiving.
Answer of Q -6
Frame Check Sequence is the process to check the correctness of the data that is
received from the sending end. In Frame Check Sequence, the data bit stream is
converted to the data frame in the data link layer and the frame will be transfer the
receiving end from the sending end. To check the data frame, division method is used.
In this section, the message bit 111010110 will be check for the consistency at the
sending and receiving end both to check whether the data contains any error while
transmission. For this checking, the pattern bit 101110 is required by which the division
will be done on the message bit (Hai Xue, 2018). For each checking, the remainder
will be into consideration and checked at both sides. If the check it will be same at both
sides then 111010110 will be accepted and otherwise will be rejected.
The process of the two ends are shown below:
12. As seen from the computation, the remained of the division result a both the sides will
be same and so the data will be considered to be error free and thus will be accepted.
Answer of Q -7
The following parameters are provided in the instruction:
Input message = 101
PN Sequence= 011011010110
T= 4Tc
Direct Sequence Spread Spectrum can e simply obtained by the performing XOR
operation between the message input and the PN sequence. Thus, the operation is
shown below with the output bit pattern of the Direct Sequence Spread Spectrum and
the graphical representation also (B. A. A. Nunes, 2014).
101⨁ 011011010110 = 11011010011
The output of the obtained Direct Sequence Spread Spectrum is as follows:
Answer of Q -8
There are different types of cells are there for the cellular communication like the
circular shaped cell, square shaped cell and the hexagonal shaped cell. The
comparative dis is made below to find out the accepted type of cell shape to be
appropriate with the cellular communication. The discussion is as follows:
Square Cell Circular Cell Hexagonal Cell
Distance to
the
periphery
Not equal at all the
sides of the
periphery.
It is same for all the
sides.
It is same for all the
sides.
Area
overlapped
There is no area that
overlapped with other
cell.
Overlap area or
portion is found among
the cell.
There is no area
that overlapped with
other cell.
Misuse of
information
transfer
Less amount of
information may be
misused due to
structure.
Large amount of
information may be
misused due to
structure.
Least amount of
information may be
misused due to
structure.
13. Area
unused
No unused space is
there among the
cells.
Unused space is
generated when the
cells are accumulated
together for the
operation.
No unused space is
there among the
cells.
Radiation
angle
Not same from every
point of the periphery.
Same from every point
of the periphery.
Same from every
point of the
periphery.
Shape
From the above discussion, it can be concluded that, the hexagonal cell is the most
appropriate for the cellular communication rather compared to other two.
14. References
B. A. A.Nunes,M. M. X.-N.N.K. O.a. T. T., 2014. A surveyof software-definednetworking:past,
present,andfuture of programmable networks,. IEEECommunicationsSurveys&Tutorials, 16(3), p.
1617–1634.
D. Kreutz,F.M. V.R. P. E. V.C. E. R. S. A. a. S.U., 2015. Software-definednetworking:a
comprehensive survey. Proceedingsof theIEEE, 103(1), p. 14–76.
Hai Xue,K.T. K. a. H. Y. Y., 2018. PacketSchedulingforMultiple-SwitchSoftware-Defined
NetworkinginEdge ComputingEnvironment. WirelessCommunicationsand MobileComputing,
Volume 2018.
Pandya,M. P. a. A.,2017. Edge Computing:DesignaFrameworkforMonitoringPerformance
betweenDatacentersandDevicesof Edge Networks. InternationalJournalof Computer&
MathematicalSciences, 6(6), p.73–77.
Woensel,F.R.B. C. a. T. V.,2014. Finite queueingmodelingandoptimization:A selectedreview,.
Journalof Applied Mathematics, Volume2014.
