SlideShare une entreprise Scribd logo
1  sur  14
Data Representation

3-1

Data Types
 Binary information is stored in memory or processor registers
 Registers contain either data or control information
Data are numbers and other binary-coded information
Control information is a bit or a group of bits used to specify the sequence
of command signals

 Data types found in the registers of digital computers
Numbers used in arithmetic computations
Letters of the alphabet used in data processing
Other discrete symbols used for specific purpose
» Number , Letter, gray code, error detection code, …

 Number Systems
Base or Radix r system : uses distinct symbols for r digits
Most common number system :Decimal, Binary, Octal, Hexadecimal
Positional-value(weight) System : r2 r 1r0.r-1 r-2 r-3
» Multiply each digit by an integer power of r and then form he sum of all weighted
digits

Computer System Architecture

Chap. 3 Data Representation

Dept. of Info. Of Computer
3-2

 Decimal System/Base-10 System
Composed of 10 symbols or numerals(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0)
 Binary System/Base-2 System
Composed of 10 symbols or numerals(0, 1)
Bit = Binary digit
 Hexadecimal System/Base-16 System : Tab. 3-2
Composed of 16 symbols or numerals(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D,
E, F)
 Binary-to-Decimal Conversions
1011.1012 = (1 x 23) + (0 x 22)+ (1 x 21) + (1 x 2o) + (1 x 2-1) + (0 x 2-2) + (1 x 2-3)
= 810+ 0 + 210 + 110 + 0.510 + 0 + 0.12510
= 11.62510

 Decimal-to-Binary Conversions
Repeated division
37 / 2 = 18 remainder 1 (binary number will end with 1) : LSB
18 / 2 = 9 remainder 0
9 / 2 = 4 remainder 1
4 / 2 = 2 remainder 0
2 / 2 = 1 remainder 0

0.375 x 2 = 0.750 integer
0.750 x 2 = 1.500 integer
0.500 x 2 = 1.000 integer
Read the result downward

0 MSB
1
.
1 LSB
.37510 = .0112

1 / 2 = 0 remainder 1 (binary number will start with 1) : MSB
Read the result upward to give an answer of 37 10 = 1001012

Computer System Architecture

Chap. 3 Data Representation

Dept. of Info. Of Computer
3-3

 Hex-to-Decimal Conversion
2AF16 = (2 x 162) + (10 x 161) + (15 x 16o)
= 51210 + 16010 + 1510
= 68710

 Decimal-to-Hex Conversion
42310 / 16 = 26 remainder 7 (Hex number will end with 7) : LSB
2610 / 16 = 1 remainder 10
110 / 16 = 0 remainder 1 (Hex number will start with 1) : MSB
Read the result upward to give an answer of 423 10 = 1A716

 Hex-to-Binary Conversion
9F216 =

9

F

2

Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

 Binary-to-Hex Conversion
1 1 1 0 1 0 0 1 1 02 = 0 0 1 1 1 0 1 0 0 1 1 0
3
= 3A616

= 1001 1111 0010
= 1001111100102

Computer System Architecture

Hex
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F

Chap. 3 Data Representation

A

6

Dept. of Info. Of Computer
3-4

 Binary-Coded-Decimal Code
Each digit of a decimal number is represented by its binary equivalent
8

7

4

1000

0111

0100

(Decimal)
(BCD)

Only the four bit binary numbers from 0000 through 1001 are used
Comparison of BCD and Binary
13710

= 100010012

(Binary) - require only 8 bits

13710

= 0001 0011 0111BCD (BCD) - require 12 bits

 Alphanumeric Representation
Alphanumeric character set
» 10 decimal digits, 26 letters, special character($, +, =,….)
» A complete list of ASCII : p. 384, Tab. 11-1

ASCII(American Standard Code for Information Interchange)
» Standard alphanumeric binary code uses seven bits to code 128 characters

Computer System Architecture

Chap. 3 Data Representation

Dept. of Info. Of Computer
3-5

3-2 Complements
 Complements are used in digital computers for simplifying the

subtraction operation and for logical manipulation
 There are two types of complements for base r system
1) r’s complement

2) (r-1)’s complement

» Binary number : 2’s or 1’s complement
» Decimal number : 10’s or 9’s complement

 (r-1)’s Complement
(r-1)’s Complement of N = (rn-1)-N

N : given number
r : base
n : digit number

» 9’s complement of N=546700
(106-1)-546700= (1000000-1)-546700= 999999-546700
546700(N) + 453299(9’s com)
= 453299
=999999
» 1’s complement of N=101101
(26-1)-101101= (1000000-1)-101101= 111111-101101
101101(N) + 010010(1’s com)
= 010010
=111111

 r’s Complement
r’s Complement of N = rn-N

* r’s Complement
(r-1)’s Complement +1 =(rn-1)-N+1= rn-N

» 10’s complement of 2389= 7610+1= 7611
» 2’s complement of 1101100= 0010011+1= 0010100
Computer System Architecture

Chap. 3 Data Representation

Dept. of Info. Of Computer
3-6

 Subtraction of Unsigned Numbers
(M-N), N≠0
1) M + (rn-N)
2) M ≥ N : Discard end carry, Result = M-N
3) M < N : No end carry, Result = - r’s complement of (N-M)
» Decimal Example)
M ≥ N 72532(M) - 13250(N) = 59282
M<N
72532
+ 86750 (10’s complement of 13250)
Discard
End Carry
1 59282
No End Carry
Result = 59282
» Binary Example)
X ≥ Y 1010100(X) - 1000011(Y) = 0010001
X<Y
1010100
+ 0111101 (2’s complement of 1000011)
1 0010001
Result = 0010001

Computer System Architecture

13250(M) - 72532(N) = -59282
13250
+ 27468 (10’s complement of 72532)
0 40718
Result = -(10’s complement of 40718)
= -(59281+1) = -59282
1000011(X) - 1010100(Y) = -0010001
1000011
+ 0101100 (2’s complement of 1010100)
0 1101111
Result = -(2’s complement of 1101111)
= -(0010000+1) = -0010001

Chap. 3 Data Representation

Dept. of Info. Of Computer
3-7

*Numeric Data
1) Fixed Point
2) Floating Point

3-3 Fixed-Point Representation

 Computers must represent everything with 1’s and 0’s, including the

sign of a number and fixed/floating point number
 Binary/Decimal Point

* 32.25
1) 0.25, 2) 32.0, 3) 32.25

The position of the binary/decimal point is needed to represent fractions,
integers, or mixed integer-fraction number

 Two ways of specifying the position of the binary point in a register
1) Fixed Point : the binary point is always fixed in one position
» A binary point in the extreme left of the register(Fraction : 0.xxxxx)
» A binary point in the extreme right of the register(Integer : xxxxx.0)
The binary point is not actually present, but the number stored in the register is treated
as a fraction or as an integer

2) Floating Point : the second register is used to designate the position of the
binary point in the first register(refer to 3-4)
* MSB for Sign
Most
Common

 Integer Representation
Signed-magnitude representation
Signed-1’s complement representation
Signed-2’s complement representation

Computer System Architecture

+14

-14

0 0001110

1 0001110

0 0001110

1 1110001

0 0001110

“0” is plus +
“1” is minus -

1 1110010

Chap. 3 Data Representation

Dept. of Info. Of Computer
3-8

 Arithmetic Addition
Addition Rules of Ordinary Arithmetic

(-12) + (-13) = -25
(+12) + (+13) = +25

» The signs are same : sign= common sign, result= add
» The signs are different : sign= larger sign, result= larger-smaller
*Addition Exam)
Addition Rules of the signed 2’s complement
+ 6 00000110
» Add the two numbers including their sign bits
+ 13 00001101
» Discard any carry out of the sign bit position
+ 19 00010011

 Arithmetic Subtraction
Subtraction is changed to an Addition

Discard
End Carry

» (± A) - (+ B) = (± A) + (- B)
» (± A) - ( - B) = (± A) + (+ B)
* Subtraction Exam) (- 6) - ( - 13) = +7
11111010 - 11110011 = 11111010 + 2’s comp of 11110011
= 11111010 + 00001101
= 1 00000111 = +7

+ 6 00000110
- 13 11110011
- 7 11111001

(+25) + (-37)
= 37 - 25 = -12
- 6 11111010
+ 13 00001101
+ 7 00000111
- 6 11111010
- 13 11110011
- 19 11101101

 Overflow
Two numbers of n digits each are added and the sum occupies n+1 digits
n + 1 bit cannot be accommodated in a register with a standard length of n
bits(many computer detect the occurrence of an overflow, and a
corresponding F/F is set)
Computer System Architecture

Chap. 3 Data Representation

Dept. of Info. Of Computer
3-9

 Overflow
An overflow may occur if the two numbers added are both positive or both
negative
» When two unsigned numbers are added
an overflow is detected from the end carry out of the MSB position

» When two signed numbers are added
the MSB always represents the sign
- the sign bit is treated as part of the number
- the end carry does not indicate an overflow

* Overflow Exam)
out in
out
carries 0 1
carries 1
+ 70 0 1000110 - 70
+ 80 0 1010000 - 80
+ 150 1 0010110 - 150

in
0
1 0111010
1 0110000
0 1101010

 Overflow Detection
Detected by observing the carry into the sign bit position and the carry out
of the sign bit position
If these two carries are not equal, an overflow
*Decimal Exam) (+375) + (-240)
condition is produced(Exclusive-OR gate = 1) 375 + (10’s comp of 240)= 375 + 760
 Decimal Fixed-Point Representation
0 375 (0000 0011 0111 0101)
* Advantage *
Computer I/O data
are generated by
people who use
the decimal
system

+9 760 (1001 0111 0110 0000)
A 4 bit decimal code requires four F/Fs
0 135 (0000 0001 0011 0101)
for each decimal digit
The representation of 4385 in BCD requires 16 F/Fs (0100 0011 1000 0101)
The representation in decimal is wasting a considerable amount of storage
space and the circuits required to perform decimal arithmetic are more
complex

Computer System Architecture

Chap. 3 Data Representation

Dept. of Info. Of Computer
3-10

3-4 Floating-Point Representation
 The floating-point representation of a number has two parts
* Decimal + 6132.789
1) Mantissa : signed, fixed-point number
Fraction
Exponent
2) Exponent : position of binary(decimal) point
+0.6132789
+4
 Scientific notation : m x re (+0.6132789 x 10+4)
m : mantissa, r : radix, e : exponent

 Example : m x 2e = +(.1001110)2 x 2+4

Fraction
01001110

Exponent
000100

 Normalization
Most significant digit of mantissa is nonzero

3-5 Other Binary Codes
 Gray Code
Gray code changes by only one bit (Tab. 3-5 4-bit Gray Code )
용도 :
» The data must be converted into digital form before they can be used by a digital
computer(Analog to Digital Converter)
» The analog data are represented by the continuous change of a shaft
position(Rotary Encoder of Motor)

Computer System Architecture

Chap. 3 Data Representation

Dept. of Info. Of Computer
3-11

 Other Decimal Codes
Binary codes for decimal digits require four bits. A few possibilities are
shown in Tab. 3-6
Excess-3 Gray Code
» Gray code 로 BCD 표현 시 , 9 에서 0 으로 변하면 1101 에서 0000 으로 되어
3 비트가 동시에 변경되어 Tab. 3-5 에서 3 부터 12 까지 사용하면 0010 에서
1010 되어 1 비트가 바뀜 .

Self-Complementing : excess-3 code
» 9’s complement of a decimal number is easily obtained by 1’s
* Self-Complement Exam)
complement(=changing 1’s to 0’s and 0’s to 1’s)
410 = 0111 (3-excess)
Weighted Code : 2421 code
= 1000 ( 1’s comp)
» The bits are multiplied by the weights, and the sum
= 510 (3-excess in Tab. 3-6)
of the weighted bits gives the decimal digit
= 510( 9’s comp of 4)

 Other Alphanumeric Codes
ASCII Code
» Format effector : Functional characters for controlling the layout of printing or
display devices(carriage return-CR, line feed-LF, horizontal tab-HT,…)
» Data communication flow control(acknowledge-ACK, escape-ESC, synchronousSYN,…)

EBCDIC(Extended BCD Interchange Code)
» Used in IBM equipment
Computer System Architecture

Chap. 3 Data Representation

Dept. of Info. Of Computer
3-12

3-6 Error Detection Codes
 Binary information transmitted through some form of communication

Transmitter

~

medium is subject to external noise
×

Receiver

 Parity Bit
An extra bit included with a binary message to make the total number of 1’s
either odd or even(Tab. 3-7)
 Even-parity method
The value of the parity bit is chosen so that the total number of 1s (including
the parity bit) is an even number

1 1 0 0 0 0 1 1
Added parity bit

 Odd-parity method
Exactly the same way except that the total number of 1s is an odd number

1 1 0 0 0 0 0 1
Added parity bit
Computer System Architecture

Chap. 3 Data Representation

Dept. of Info. Of Computer
3-13

 Parity Generator/Checker
At the sending end, the message is applied to a parity generator
At the receiving end, all the incoming bits are applied to a parity checker
1 1 0 0 0 0 1 1 “C”
(Even-parity Generator)

1 1 0 0 0 0 1 0 ”B”
(Even-parity Checker)

Can not tell which bit in error
Can detect only single bit error(odd number of errors)
3 bit data line example : Fig. 3-3

 4 bit data line example :

Next Page

Computer System Architecture

Chap. 3 Data Representation

Dept. of Info. Of Computer
3-14

Odd Parity Generator/Checker
 Truth Table
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

E
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0

O
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1

 K-Map(Odd Parity)
C

0

3

2

4

5

7

6

12

13

15

14

8

A

1

9

11

10

B

D

 Expression
A B C D + A B CD + A BC D + A BCD + ABC D + ABCD + AB C D + AB CD
= A B (C D + CD ) + A B(C D + CD ) + AB (C D + CD ) + AB (C D + CD )
= A B (C ⊗ D ) + A B(C ⊕ D ) + AB (C ⊗ D ) + AB (C ⊕ D )
= (C ⊗ D )( A B + AB ) + (C ⊕ D )( A B + AB )
= (C ⊗ D )( A ⊗ B ) + (C ⊕ D )( A ⊕ B )
= (C ⊕ D )( A ⊕ B ) + (C ⊕ D )( A ⊕ B )
= x y + xy

⊕ : XOR
⊗ : XNOR

x =C⊕D
y = A⊕ B

= x⊗ y
= x⊕ y
= (C ⊕ D ) ⊕ ( A ⊕ B )
= C ⊕ D ⊕ A⊕ B
Computer System Architecture

Chap. 3 Data Representation

Dept. of Info. Of Computer

Contenu connexe

Tendances

Chapter 03 arithmetic for computers
Chapter 03   arithmetic for computersChapter 03   arithmetic for computers
Chapter 03 arithmetic for computers
Bảo Hoang
 
Chapter 03 number system
Chapter 03 number systemChapter 03 number system
Chapter 03 number system
IIUI
 

Tendances (20)

Digital Logic & Design
Digital Logic & DesignDigital Logic & Design
Digital Logic & Design
 
Data Reprersentation
Data Reprersentation  Data Reprersentation
Data Reprersentation
 
Chapter 03 arithmetic for computers
Chapter 03   arithmetic for computersChapter 03   arithmetic for computers
Chapter 03 arithmetic for computers
 
Stld
StldStld
Stld
 
Digital Components
Digital ComponentsDigital Components
Digital Components
 
DESIGN OF COMBINATIONAL LOGIC
DESIGN OF COMBINATIONAL LOGICDESIGN OF COMBINATIONAL LOGIC
DESIGN OF COMBINATIONAL LOGIC
 
Lcdf4 chap 03_p2
Lcdf4 chap 03_p2Lcdf4 chap 03_p2
Lcdf4 chap 03_p2
 
Chapter 03 number system
Chapter 03 number systemChapter 03 number system
Chapter 03 number system
 
Logic Design
Logic DesignLogic Design
Logic Design
 
Digital Logic circuit
Digital Logic circuitDigital Logic circuit
Digital Logic circuit
 
Lecture 01 dld 2018
Lecture 01 dld  2018Lecture 01 dld  2018
Lecture 01 dld 2018
 
Unit 2 Arithmetic
Unit 2 ArithmeticUnit 2 Arithmetic
Unit 2 Arithmetic
 
Combinational circuits
Combinational circuits Combinational circuits
Combinational circuits
 
STLD-Combinational logic design
STLD-Combinational  logic design STLD-Combinational  logic design
STLD-Combinational logic design
 
Arithmetic & Logic Unit
Arithmetic & Logic UnitArithmetic & Logic Unit
Arithmetic & Logic Unit
 
Ch1 2
Ch1 2Ch1 2
Ch1 2
 
Combinational logic
Combinational logicCombinational logic
Combinational logic
 
B sc cs i bo-de u-iii combitional logic circuit
B sc cs i bo-de u-iii combitional logic circuitB sc cs i bo-de u-iii combitional logic circuit
B sc cs i bo-de u-iii combitional logic circuit
 
Mcsl 17 ALP lab manual
Mcsl 17 ALP lab manualMcsl 17 ALP lab manual
Mcsl 17 ALP lab manual
 
Combinational Logic Circuits
Combinational Logic CircuitsCombinational Logic Circuits
Combinational Logic Circuits
 

Similaire à Computer organiztion2

Similaire à Computer organiztion2 (20)

Data representation
Data representationData representation
Data representation
 
Datarepresentation2
Datarepresentation2Datarepresentation2
Datarepresentation2
 
Data representation moris mano ch 03
Data representation   moris mano ch  03Data representation   moris mano ch  03
Data representation moris mano ch 03
 
Ch3
Ch3Ch3
Ch3
 
DATA REPRESENTATION
DATA  REPRESENTATIONDATA  REPRESENTATION
DATA REPRESENTATION
 
Unit-6 Computer Arithmetic.ppsx
Unit-6 Computer Arithmetic.ppsxUnit-6 Computer Arithmetic.ppsx
Unit-6 Computer Arithmetic.ppsx
 
Okkkkk
OkkkkkOkkkkk
Okkkkk
 
DLD-Introduction.pptx
DLD-Introduction.pptxDLD-Introduction.pptx
DLD-Introduction.pptx
 
Number_Systems (2).ppt
Number_Systems (2).pptNumber_Systems (2).ppt
Number_Systems (2).ppt
 
Chapter_1_Digital_Systems_and_Binary_Numbers2.ppt
Chapter_1_Digital_Systems_and_Binary_Numbers2.pptChapter_1_Digital_Systems_and_Binary_Numbers2.ppt
Chapter_1_Digital_Systems_and_Binary_Numbers2.ppt
 
Number system and codes
Number system and codesNumber system and codes
Number system and codes
 
DCF QNA edited
DCF QNA editedDCF QNA edited
DCF QNA edited
 
digital-systems-and-binary-numbers1.pptx
digital-systems-and-binary-numbers1.pptxdigital-systems-and-binary-numbers1.pptx
digital-systems-and-binary-numbers1.pptx
 
Module 1 number systems and code1
Module 1  number systems and code1Module 1  number systems and code1
Module 1 number systems and code1
 
Chapter 1 Digital Systems and Binary Numbers.ppt
Chapter 1 Digital Systems and Binary Numbers.pptChapter 1 Digital Systems and Binary Numbers.ppt
Chapter 1 Digital Systems and Binary Numbers.ppt
 
Video lectures
Video lecturesVideo lectures
Video lectures
 
Mba ebooks
Mba ebooksMba ebooks
Mba ebooks
 
Unit 1 PDF.pptx
Unit 1 PDF.pptxUnit 1 PDF.pptx
Unit 1 PDF.pptx
 
Chapter 1 digital design.pptx
Chapter 1 digital design.pptxChapter 1 digital design.pptx
Chapter 1 digital design.pptx
 
W 9 numbering system
W 9 numbering systemW 9 numbering system
W 9 numbering system
 

Plus de Umang Gupta

23 network security threats pkg
23 network security threats pkg23 network security threats pkg
23 network security threats pkg
Umang Gupta
 
Chapter8 27 nov_2010
Chapter8 27 nov_2010Chapter8 27 nov_2010
Chapter8 27 nov_2010
Umang Gupta
 
Lecture43 network security
Lecture43 network securityLecture43 network security
Lecture43 network security
Umang Gupta
 
11. transaction sql
11. transaction sql11. transaction sql
11. transaction sql
Umang Gupta
 
Advanced data structures and implementation
Advanced data structures and implementationAdvanced data structures and implementation
Advanced data structures and implementation
Umang Gupta
 
Graph theory narsingh deo
Graph theory narsingh deoGraph theory narsingh deo
Graph theory narsingh deo
Umang Gupta
 
Computer organiztion6
Computer organiztion6Computer organiztion6
Computer organiztion6
Umang Gupta
 
Computer organiztion4
Computer organiztion4Computer organiztion4
Computer organiztion4
Umang Gupta
 
Computer organiztion1
Computer organiztion1Computer organiztion1
Computer organiztion1
Umang Gupta
 
Computer organiztion5
Computer organiztion5Computer organiztion5
Computer organiztion5
Umang Gupta
 
Angle modulation
Angle modulationAngle modulation
Angle modulation
Umang Gupta
 
periodic functions and Fourier series
periodic functions and Fourier seriesperiodic functions and Fourier series
periodic functions and Fourier series
Umang Gupta
 
fourier transforms
fourier transformsfourier transforms
fourier transforms
Umang Gupta
 
Communication systems
Communication systemsCommunication systems
Communication systems
Umang Gupta
 

Plus de Umang Gupta (16)

23 network security threats pkg
23 network security threats pkg23 network security threats pkg
23 network security threats pkg
 
Lect13 security
Lect13   securityLect13   security
Lect13 security
 
Chapter8 27 nov_2010
Chapter8 27 nov_2010Chapter8 27 nov_2010
Chapter8 27 nov_2010
 
Lecture43 network security
Lecture43 network securityLecture43 network security
Lecture43 network security
 
11. transaction sql
11. transaction sql11. transaction sql
11. transaction sql
 
Advanced data structures and implementation
Advanced data structures and implementationAdvanced data structures and implementation
Advanced data structures and implementation
 
Graph theory narsingh deo
Graph theory narsingh deoGraph theory narsingh deo
Graph theory narsingh deo
 
Computer organiztion6
Computer organiztion6Computer organiztion6
Computer organiztion6
 
Computer organiztion4
Computer organiztion4Computer organiztion4
Computer organiztion4
 
Computer organiztion1
Computer organiztion1Computer organiztion1
Computer organiztion1
 
Computer organiztion5
Computer organiztion5Computer organiztion5
Computer organiztion5
 
Angle modulation
Angle modulationAngle modulation
Angle modulation
 
periodic functions and Fourier series
periodic functions and Fourier seriesperiodic functions and Fourier series
periodic functions and Fourier series
 
fourier transforms
fourier transformsfourier transforms
fourier transforms
 
Basic antenas
Basic antenasBasic antenas
Basic antenas
 
Communication systems
Communication systemsCommunication systems
Communication systems
 

Dernier

1029-Danh muc Sach Giao Khoa khoi 6.pdf
1029-Danh muc Sach Giao Khoa khoi  6.pdf1029-Danh muc Sach Giao Khoa khoi  6.pdf
1029-Danh muc Sach Giao Khoa khoi 6.pdf
QucHHunhnh
 
Making and Justifying Mathematical Decisions.pdf
Making and Justifying Mathematical Decisions.pdfMaking and Justifying Mathematical Decisions.pdf
Making and Justifying Mathematical Decisions.pdf
Chris Hunter
 
Beyond the EU: DORA and NIS 2 Directive's Global Impact
Beyond the EU: DORA and NIS 2 Directive's Global ImpactBeyond the EU: DORA and NIS 2 Directive's Global Impact
Beyond the EU: DORA and NIS 2 Directive's Global Impact
PECB
 
Seal of Good Local Governance (SGLG) 2024Final.pptx
Seal of Good Local Governance (SGLG) 2024Final.pptxSeal of Good Local Governance (SGLG) 2024Final.pptx
Seal of Good Local Governance (SGLG) 2024Final.pptx
negromaestrong
 

Dernier (20)

Accessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impactAccessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impact
 
Measures of Central Tendency: Mean, Median and Mode
Measures of Central Tendency: Mean, Median and ModeMeasures of Central Tendency: Mean, Median and Mode
Measures of Central Tendency: Mean, Median and Mode
 
psychiatric nursing HISTORY COLLECTION .docx
psychiatric  nursing HISTORY  COLLECTION  .docxpsychiatric  nursing HISTORY  COLLECTION  .docx
psychiatric nursing HISTORY COLLECTION .docx
 
Sports & Fitness Value Added Course FY..
Sports & Fitness Value Added Course FY..Sports & Fitness Value Added Course FY..
Sports & Fitness Value Added Course FY..
 
Z Score,T Score, Percential Rank and Box Plot Graph
Z Score,T Score, Percential Rank and Box Plot GraphZ Score,T Score, Percential Rank and Box Plot Graph
Z Score,T Score, Percential Rank and Box Plot Graph
 
Holdier Curriculum Vitae (April 2024).pdf
Holdier Curriculum Vitae (April 2024).pdfHoldier Curriculum Vitae (April 2024).pdf
Holdier Curriculum Vitae (April 2024).pdf
 
microwave assisted reaction. General introduction
microwave assisted reaction. General introductionmicrowave assisted reaction. General introduction
microwave assisted reaction. General introduction
 
Unit-IV- Pharma. Marketing Channels.pptx
Unit-IV- Pharma. Marketing Channels.pptxUnit-IV- Pharma. Marketing Channels.pptx
Unit-IV- Pharma. Marketing Channels.pptx
 
Mehran University Newsletter Vol-X, Issue-I, 2024
Mehran University Newsletter Vol-X, Issue-I, 2024Mehran University Newsletter Vol-X, Issue-I, 2024
Mehran University Newsletter Vol-X, Issue-I, 2024
 
INDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptx
INDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptxINDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptx
INDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptx
 
Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"
Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"
Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"
 
Class 11th Physics NEET formula sheet pdf
Class 11th Physics NEET formula sheet pdfClass 11th Physics NEET formula sheet pdf
Class 11th Physics NEET formula sheet pdf
 
Basic Civil Engineering first year Notes- Chapter 4 Building.pptx
Basic Civil Engineering first year Notes- Chapter 4 Building.pptxBasic Civil Engineering first year Notes- Chapter 4 Building.pptx
Basic Civil Engineering first year Notes- Chapter 4 Building.pptx
 
Nutritional Needs Presentation - HLTH 104
Nutritional Needs Presentation - HLTH 104Nutritional Needs Presentation - HLTH 104
Nutritional Needs Presentation - HLTH 104
 
1029-Danh muc Sach Giao Khoa khoi 6.pdf
1029-Danh muc Sach Giao Khoa khoi  6.pdf1029-Danh muc Sach Giao Khoa khoi  6.pdf
1029-Danh muc Sach Giao Khoa khoi 6.pdf
 
Grant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy ConsultingGrant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy Consulting
 
Making and Justifying Mathematical Decisions.pdf
Making and Justifying Mathematical Decisions.pdfMaking and Justifying Mathematical Decisions.pdf
Making and Justifying Mathematical Decisions.pdf
 
Beyond the EU: DORA and NIS 2 Directive's Global Impact
Beyond the EU: DORA and NIS 2 Directive's Global ImpactBeyond the EU: DORA and NIS 2 Directive's Global Impact
Beyond the EU: DORA and NIS 2 Directive's Global Impact
 
ICT Role in 21st Century Education & its Challenges.pptx
ICT Role in 21st Century Education & its Challenges.pptxICT Role in 21st Century Education & its Challenges.pptx
ICT Role in 21st Century Education & its Challenges.pptx
 
Seal of Good Local Governance (SGLG) 2024Final.pptx
Seal of Good Local Governance (SGLG) 2024Final.pptxSeal of Good Local Governance (SGLG) 2024Final.pptx
Seal of Good Local Governance (SGLG) 2024Final.pptx
 

Computer organiztion2

  • 1. Data Representation 3-1 Data Types  Binary information is stored in memory or processor registers  Registers contain either data or control information Data are numbers and other binary-coded information Control information is a bit or a group of bits used to specify the sequence of command signals  Data types found in the registers of digital computers Numbers used in arithmetic computations Letters of the alphabet used in data processing Other discrete symbols used for specific purpose » Number , Letter, gray code, error detection code, …  Number Systems Base or Radix r system : uses distinct symbols for r digits Most common number system :Decimal, Binary, Octal, Hexadecimal Positional-value(weight) System : r2 r 1r0.r-1 r-2 r-3 » Multiply each digit by an integer power of r and then form he sum of all weighted digits Computer System Architecture Chap. 3 Data Representation Dept. of Info. Of Computer
  • 2. 3-2  Decimal System/Base-10 System Composed of 10 symbols or numerals(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0)  Binary System/Base-2 System Composed of 10 symbols or numerals(0, 1) Bit = Binary digit  Hexadecimal System/Base-16 System : Tab. 3-2 Composed of 16 symbols or numerals(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F)  Binary-to-Decimal Conversions 1011.1012 = (1 x 23) + (0 x 22)+ (1 x 21) + (1 x 2o) + (1 x 2-1) + (0 x 2-2) + (1 x 2-3) = 810+ 0 + 210 + 110 + 0.510 + 0 + 0.12510 = 11.62510  Decimal-to-Binary Conversions Repeated division 37 / 2 = 18 remainder 1 (binary number will end with 1) : LSB 18 / 2 = 9 remainder 0 9 / 2 = 4 remainder 1 4 / 2 = 2 remainder 0 2 / 2 = 1 remainder 0 0.375 x 2 = 0.750 integer 0.750 x 2 = 1.500 integer 0.500 x 2 = 1.000 integer Read the result downward 0 MSB 1 . 1 LSB .37510 = .0112 1 / 2 = 0 remainder 1 (binary number will start with 1) : MSB Read the result upward to give an answer of 37 10 = 1001012 Computer System Architecture Chap. 3 Data Representation Dept. of Info. Of Computer
  • 3. 3-3  Hex-to-Decimal Conversion 2AF16 = (2 x 162) + (10 x 161) + (15 x 16o) = 51210 + 16010 + 1510 = 68710  Decimal-to-Hex Conversion 42310 / 16 = 26 remainder 7 (Hex number will end with 7) : LSB 2610 / 16 = 1 remainder 10 110 / 16 = 0 remainder 1 (Hex number will start with 1) : MSB Read the result upward to give an answer of 423 10 = 1A716  Hex-to-Binary Conversion 9F216 = 9 F 2 Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15  Binary-to-Hex Conversion 1 1 1 0 1 0 0 1 1 02 = 0 0 1 1 1 0 1 0 0 1 1 0 3 = 3A616 = 1001 1111 0010 = 1001111100102 Computer System Architecture Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F Chap. 3 Data Representation A 6 Dept. of Info. Of Computer
  • 4. 3-4  Binary-Coded-Decimal Code Each digit of a decimal number is represented by its binary equivalent 8 7 4 1000 0111 0100 (Decimal) (BCD) Only the four bit binary numbers from 0000 through 1001 are used Comparison of BCD and Binary 13710 = 100010012 (Binary) - require only 8 bits 13710 = 0001 0011 0111BCD (BCD) - require 12 bits  Alphanumeric Representation Alphanumeric character set » 10 decimal digits, 26 letters, special character($, +, =,….) » A complete list of ASCII : p. 384, Tab. 11-1 ASCII(American Standard Code for Information Interchange) » Standard alphanumeric binary code uses seven bits to code 128 characters Computer System Architecture Chap. 3 Data Representation Dept. of Info. Of Computer
  • 5. 3-5 3-2 Complements  Complements are used in digital computers for simplifying the subtraction operation and for logical manipulation  There are two types of complements for base r system 1) r’s complement 2) (r-1)’s complement » Binary number : 2’s or 1’s complement » Decimal number : 10’s or 9’s complement  (r-1)’s Complement (r-1)’s Complement of N = (rn-1)-N N : given number r : base n : digit number » 9’s complement of N=546700 (106-1)-546700= (1000000-1)-546700= 999999-546700 546700(N) + 453299(9’s com) = 453299 =999999 » 1’s complement of N=101101 (26-1)-101101= (1000000-1)-101101= 111111-101101 101101(N) + 010010(1’s com) = 010010 =111111  r’s Complement r’s Complement of N = rn-N * r’s Complement (r-1)’s Complement +1 =(rn-1)-N+1= rn-N » 10’s complement of 2389= 7610+1= 7611 » 2’s complement of 1101100= 0010011+1= 0010100 Computer System Architecture Chap. 3 Data Representation Dept. of Info. Of Computer
  • 6. 3-6  Subtraction of Unsigned Numbers (M-N), N≠0 1) M + (rn-N) 2) M ≥ N : Discard end carry, Result = M-N 3) M < N : No end carry, Result = - r’s complement of (N-M) » Decimal Example) M ≥ N 72532(M) - 13250(N) = 59282 M<N 72532 + 86750 (10’s complement of 13250) Discard End Carry 1 59282 No End Carry Result = 59282 » Binary Example) X ≥ Y 1010100(X) - 1000011(Y) = 0010001 X<Y 1010100 + 0111101 (2’s complement of 1000011) 1 0010001 Result = 0010001 Computer System Architecture 13250(M) - 72532(N) = -59282 13250 + 27468 (10’s complement of 72532) 0 40718 Result = -(10’s complement of 40718) = -(59281+1) = -59282 1000011(X) - 1010100(Y) = -0010001 1000011 + 0101100 (2’s complement of 1010100) 0 1101111 Result = -(2’s complement of 1101111) = -(0010000+1) = -0010001 Chap. 3 Data Representation Dept. of Info. Of Computer
  • 7. 3-7 *Numeric Data 1) Fixed Point 2) Floating Point 3-3 Fixed-Point Representation  Computers must represent everything with 1’s and 0’s, including the sign of a number and fixed/floating point number  Binary/Decimal Point * 32.25 1) 0.25, 2) 32.0, 3) 32.25 The position of the binary/decimal point is needed to represent fractions, integers, or mixed integer-fraction number  Two ways of specifying the position of the binary point in a register 1) Fixed Point : the binary point is always fixed in one position » A binary point in the extreme left of the register(Fraction : 0.xxxxx) » A binary point in the extreme right of the register(Integer : xxxxx.0) The binary point is not actually present, but the number stored in the register is treated as a fraction or as an integer 2) Floating Point : the second register is used to designate the position of the binary point in the first register(refer to 3-4) * MSB for Sign Most Common  Integer Representation Signed-magnitude representation Signed-1’s complement representation Signed-2’s complement representation Computer System Architecture +14 -14 0 0001110 1 0001110 0 0001110 1 1110001 0 0001110 “0” is plus + “1” is minus - 1 1110010 Chap. 3 Data Representation Dept. of Info. Of Computer
  • 8. 3-8  Arithmetic Addition Addition Rules of Ordinary Arithmetic (-12) + (-13) = -25 (+12) + (+13) = +25 » The signs are same : sign= common sign, result= add » The signs are different : sign= larger sign, result= larger-smaller *Addition Exam) Addition Rules of the signed 2’s complement + 6 00000110 » Add the two numbers including their sign bits + 13 00001101 » Discard any carry out of the sign bit position + 19 00010011  Arithmetic Subtraction Subtraction is changed to an Addition Discard End Carry » (± A) - (+ B) = (± A) + (- B) » (± A) - ( - B) = (± A) + (+ B) * Subtraction Exam) (- 6) - ( - 13) = +7 11111010 - 11110011 = 11111010 + 2’s comp of 11110011 = 11111010 + 00001101 = 1 00000111 = +7 + 6 00000110 - 13 11110011 - 7 11111001 (+25) + (-37) = 37 - 25 = -12 - 6 11111010 + 13 00001101 + 7 00000111 - 6 11111010 - 13 11110011 - 19 11101101  Overflow Two numbers of n digits each are added and the sum occupies n+1 digits n + 1 bit cannot be accommodated in a register with a standard length of n bits(many computer detect the occurrence of an overflow, and a corresponding F/F is set) Computer System Architecture Chap. 3 Data Representation Dept. of Info. Of Computer
  • 9. 3-9  Overflow An overflow may occur if the two numbers added are both positive or both negative » When two unsigned numbers are added an overflow is detected from the end carry out of the MSB position » When two signed numbers are added the MSB always represents the sign - the sign bit is treated as part of the number - the end carry does not indicate an overflow * Overflow Exam) out in out carries 0 1 carries 1 + 70 0 1000110 - 70 + 80 0 1010000 - 80 + 150 1 0010110 - 150 in 0 1 0111010 1 0110000 0 1101010  Overflow Detection Detected by observing the carry into the sign bit position and the carry out of the sign bit position If these two carries are not equal, an overflow *Decimal Exam) (+375) + (-240) condition is produced(Exclusive-OR gate = 1) 375 + (10’s comp of 240)= 375 + 760  Decimal Fixed-Point Representation 0 375 (0000 0011 0111 0101) * Advantage * Computer I/O data are generated by people who use the decimal system +9 760 (1001 0111 0110 0000) A 4 bit decimal code requires four F/Fs 0 135 (0000 0001 0011 0101) for each decimal digit The representation of 4385 in BCD requires 16 F/Fs (0100 0011 1000 0101) The representation in decimal is wasting a considerable amount of storage space and the circuits required to perform decimal arithmetic are more complex Computer System Architecture Chap. 3 Data Representation Dept. of Info. Of Computer
  • 10. 3-10 3-4 Floating-Point Representation  The floating-point representation of a number has two parts * Decimal + 6132.789 1) Mantissa : signed, fixed-point number Fraction Exponent 2) Exponent : position of binary(decimal) point +0.6132789 +4  Scientific notation : m x re (+0.6132789 x 10+4) m : mantissa, r : radix, e : exponent  Example : m x 2e = +(.1001110)2 x 2+4 Fraction 01001110 Exponent 000100  Normalization Most significant digit of mantissa is nonzero 3-5 Other Binary Codes  Gray Code Gray code changes by only one bit (Tab. 3-5 4-bit Gray Code ) 용도 : » The data must be converted into digital form before they can be used by a digital computer(Analog to Digital Converter) » The analog data are represented by the continuous change of a shaft position(Rotary Encoder of Motor) Computer System Architecture Chap. 3 Data Representation Dept. of Info. Of Computer
  • 11. 3-11  Other Decimal Codes Binary codes for decimal digits require four bits. A few possibilities are shown in Tab. 3-6 Excess-3 Gray Code » Gray code 로 BCD 표현 시 , 9 에서 0 으로 변하면 1101 에서 0000 으로 되어 3 비트가 동시에 변경되어 Tab. 3-5 에서 3 부터 12 까지 사용하면 0010 에서 1010 되어 1 비트가 바뀜 . Self-Complementing : excess-3 code » 9’s complement of a decimal number is easily obtained by 1’s * Self-Complement Exam) complement(=changing 1’s to 0’s and 0’s to 1’s) 410 = 0111 (3-excess) Weighted Code : 2421 code = 1000 ( 1’s comp) » The bits are multiplied by the weights, and the sum = 510 (3-excess in Tab. 3-6) of the weighted bits gives the decimal digit = 510( 9’s comp of 4)  Other Alphanumeric Codes ASCII Code » Format effector : Functional characters for controlling the layout of printing or display devices(carriage return-CR, line feed-LF, horizontal tab-HT,…) » Data communication flow control(acknowledge-ACK, escape-ESC, synchronousSYN,…) EBCDIC(Extended BCD Interchange Code) » Used in IBM equipment Computer System Architecture Chap. 3 Data Representation Dept. of Info. Of Computer
  • 12. 3-12 3-6 Error Detection Codes  Binary information transmitted through some form of communication Transmitter ~ medium is subject to external noise × Receiver  Parity Bit An extra bit included with a binary message to make the total number of 1’s either odd or even(Tab. 3-7)  Even-parity method The value of the parity bit is chosen so that the total number of 1s (including the parity bit) is an even number 1 1 0 0 0 0 1 1 Added parity bit  Odd-parity method Exactly the same way except that the total number of 1s is an odd number 1 1 0 0 0 0 0 1 Added parity bit Computer System Architecture Chap. 3 Data Representation Dept. of Info. Of Computer
  • 13. 3-13  Parity Generator/Checker At the sending end, the message is applied to a parity generator At the receiving end, all the incoming bits are applied to a parity checker 1 1 0 0 0 0 1 1 “C” (Even-parity Generator) 1 1 0 0 0 0 1 0 ”B” (Even-parity Checker) Can not tell which bit in error Can detect only single bit error(odd number of errors) 3 bit data line example : Fig. 3-3  4 bit data line example : Next Page Computer System Architecture Chap. 3 Data Representation Dept. of Info. Of Computer
  • 14. 3-14 Odd Parity Generator/Checker  Truth Table A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 E 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 O 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1  K-Map(Odd Parity) C 0 3 2 4 5 7 6 12 13 15 14 8 A 1 9 11 10 B D  Expression A B C D + A B CD + A BC D + A BCD + ABC D + ABCD + AB C D + AB CD = A B (C D + CD ) + A B(C D + CD ) + AB (C D + CD ) + AB (C D + CD ) = A B (C ⊗ D ) + A B(C ⊕ D ) + AB (C ⊗ D ) + AB (C ⊕ D ) = (C ⊗ D )( A B + AB ) + (C ⊕ D )( A B + AB ) = (C ⊗ D )( A ⊗ B ) + (C ⊕ D )( A ⊕ B ) = (C ⊕ D )( A ⊕ B ) + (C ⊕ D )( A ⊕ B ) = x y + xy ⊕ : XOR ⊗ : XNOR x =C⊕D y = A⊕ B = x⊗ y = x⊕ y = (C ⊕ D ) ⊕ ( A ⊕ B ) = C ⊕ D ⊕ A⊕ B Computer System Architecture Chap. 3 Data Representation Dept. of Info. Of Computer