DE notes

Digital logic
K. Adisesha, Lecturer,
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Digital Logic
Digital or binary logic has fascinated many people over the years. The very idea that a two-valued
number system can possibly be the basis for the most powerful and sophisticated computers seems
astounding, to say the least. Nevertheless, it is so, and the how and the why of this requires some
explanation.
Everything in the digital world is based on the binary number system. Numerically, this involves only
two symbols: 0 and 1. Logically, we can use these symbols or we can equate them with others according
to the needs of the moment. Thus, when dealing with digital logic, we can specify that:
0 = false = no
1 = true = yes
Using this two-valued logic system, every statement or condition must be either "true" or "false;" it
cannot be partly true and partly false. While this approach may seem limited, it actually works quite
nicely, and can be expanded to express very complex relationships and interactions among any number
of individual conditions.
One essential reason for basing logical operations on the binary number system is that it is easy to
design simple, stable electronic circuits that can switch back and forth between two clearly-defined
states, with no ambiguity attached. It is also readily possible to design and build circuits that will remain
indefinitely in one state unless and until they are deliberately switched to the other state. This makes it
possible to construct a machine (the computer) which can remember sequences of events and adjust its
behavior accordingly.
Digital logic may be divided into two classes: combinational logic, in which the logical outputs are
determined by the logical function being performed and the logical input states at that particular
moment; and sequential logic, in which the outputs also depend on the prior states of those outputs. Both
classes of logic are used extensively in all digital computers.
Since both types of logic circuits begin with logic gates to combine logical input signals in various ways
to produce the desired outputs, we will begin on the next page by seeing how the basic logic gates work.
Boolean Algebra
The most obvious way to simplify Boolean expressions is to manipulate them in the same way as normal
algebraic expressions are manipulated. With regards to logic relations in digital forms, a set of rules for
symbolic manipulation is needed in order to solve for the unknowns.
A set of rules formulated by the English mathematician George Boole describe certain propositions
whose outcome would be either true or false. With regard to digital logic, these rules are used to
describe circuits whose state can be either, 1 (true) or 0 (false). In order to fully understand this, the
relation between the AND gate, OR gate and NOT gate operations should be appreciated.
Laws of Boolean Algebra

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The basic Boolean laws. Note that every law has two expressions, (a) and (b). This is known as duality.
These are obtained by changing every AND(.) to OR(+), every OR(+) to AND(.) and all 1's to 0's and
vice-versa.
It has become conventional to drop the . (AND symbol) i.e. A.B is written as AB.
T1 : Commutative Law
(a) A + B = B + A
(b) A B = B A
T2 : Associate Law
(a) (A + B) + C = A + (B + C)
(b) (A B) C = A (B C)
T3 : Distributive Law
(a) A (B + C) = A B + A C
(b) A + (B C) = (A + B) (A + C)
T4 : Identity Law
(a) A + A = A
(b) A A = A
T5 :
(a)
(b)
T6 : Redundance Law
(a) A + A B = A
(b) A (A + B) = A
T7 :
(a) 0 + A = A
(b) 0 A = 0
T8 :
(a) 1 + A = 1
(b) 1 A = A
T9 :
(a)
(b)
T10 :
(a)
(b)
T11 : De Morgan's Theorem
(a)
(b)
Examples

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(a)
(1) Algebraically:
(2) Using the truth table:
Using the laws given above, complicated expressions can be simplified.
Boolean functions may be practically implemented by using electronic gates. The following points are
important to understand.
• Electronic gates require a power supply.
• Gate INPUTS are driven by voltages having two nominal values, e.g. 0V and 5V
representing logic 0 and logic 1 respectively.
• The OUTPUT of a gate provides two nominal values of voltage only, e.g. 0V and 5V
representing logic 0 and logic 1 respectively. In general, there is only one output to a
logic gate except in some special cases.
• There is always a time delay between an input being applied and the output responding.
Truth Tables
Truth tables are used to help show the function of a logic gate. If you are unsure about truth tables and
need guidence on how go about drawning them for individual gates or logic circuits then use the truth
table section link.
Logic gates
Digital systems are said to be constructed by using logic gates. These gates are the AND, OR, NOT,
NAND, NOR, EXOR and EXNOR gates. The basic operations are described below with the aid of truth
tables.

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AND gate
The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high.
A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes
omitted i.e. AB
OR gate
The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are
high. A plus (+) is used to show the OR operation.
NOT gate
The NOT gate is an electronic circuit that produces an inverted version of the input at its output.
It is also known as an inverter. If the input variable is A, the inverted output is known as NOT
A. This is also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams
below show two ways that the NAND logic gate can be configured to produce a NOT gate. It can
also be done using NOR logic gates in the same way.
NAND gate
This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all
NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the
output. The small circle represents inversion.
NOR gate

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This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR
gates are low if any of the inputs are high.
The symbol is an OR gate with a small circle on the output. The small circle represents inversion.
EXOR gate
The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its two
inputs are high. An encircled plus sign ( ) is used to show the EOR operation.
EXNOR gate
The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output if either,
but not both, of its two inputs are high. The symbol is an EXOR gate with a small circle on the output.
The small circle represents inversion.
The NAND and NOR gates are called universal functions since with either one the AND and OR
functions and NOT can be generated.
Note:
A function in sum of products form can be implemented using NAND gates by replacing all AND and
OR gates by NAND gates.
A function in product of sums form can be implemented using NOR gates by replacing all AND and OR
gates by NOR gates.

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Table 1: Logic gate symbols
Table 2 is a summary truth table of the input/output combinations for the NOT gate together with all
possible input/output combinations for the other gate functions. Also note that a truth table with 'n'
inputs has 2n
rows. You can compare the outputs of different gates.
Table 2: Logic gates representation using the Truth table
Example
A NAND gate can be used as a NOT gate using either of the following wiring configurations.
(You can check this out using a truth table.)

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Forms and Definitions of Boolean Expressions
Numerical Representation
Take as an example the truth table of a three-variable function as shown below. Three variables, each of
which can take the values 0 or 1, yields eight possible combinations of values for which the function
may be true. These eight combinations are listed in ascending binary order and the equivalent decimal
value is also shown in the table.
Decimal
Value
A B C f
0 0 0 0 1
1 0 0 1 0
2 0 1 0 1
3 0 1 1 1
4 1 0 0 0
5 1 0 1 0
6 1 1 0 0
7 1 1 1 1
The function has a value 1 for the combinations shown, therefore:
......(1)
This can also be written as:
f(A, B, C) = 000 + 010 + 011 + 111
Note that the summation sign indicates that the terms are "OR'ed" together. The function can be further
reduced to the form:
f(A, B, C) = (000, 010, 011, 111)
It is self-evident that the binary form of a function can be written directly from the truth table.
Note:
(a) the position of the digits must not be changed
(b) the expression must be in standard sum of products form.
It follows from the last expression that the binary form can be replaced by the equivalent decimal form,
namely:
f(A, B, C) = (0,2,3,7)......(2)
Product of Sums Representation

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From the truth table given above the function has the value 0 for the combinations shown, therefore
......(3)
Writing the inverse of this function:
Applying De Morgan's Theorem we obtain:
Applying the second De Morgan's Theorem we obtain:
......(4)
The function is expressed in standard product of sums form.
Thus there are two forms of a function, one is a sum of products form (either standard or normal) as
given by expression (1), the other a product of sums form (either standard or normal) as given by
expression (4). The gate implementation of the two forms is not the same!
Examples
Consider the function:
In binary form: f(A, B, C, D) = (0101, 1011, 1100, 0000, 1010, 0111)
In decimal form: f(A, B, C, D) = (5, 11, 12, 0, 10, 7)
Minimisation of Boolean Functions
Algebraic Manipulation of Boolean Expressions
Karnaugh Maps
Tabular Method of Minimisation
What is minimisation?
In mathematics expressions are simplified for a number of reasons, for instance simpler expression are
easier to understand and easier to write down, they are also less prone to error in interpretation but, most
importantly, simplified expressions are usually more efficient and effective when implemented in
practice.

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A Boolean expression is composed of variables and terms. The simplification of Boolean expressions
can lead to more effective computer programs, algorithms and circuits.
Before continuing with this section, you should make sure you are familiar with the following topics:
• Boolean Algebra
• Basic Gates and Functions
• Forms and Definitions of Boolean Expressions
Minimisation can be achieved by a number of methods, four well known methods are:
1. Algebraic Manipulation of Boolean Expressions
2. Karnaugh Maps
3. Tabular Method of Minimisation
4. Tree reduction
Algebraic Manipulation of Boolean Expressions
This is an approach where you can transform one boolean expression into an equivalent expression by
applying Boolean Theorems.
Minimising terms and expressions can be important because electrical circuits consist of individual
components that are implemented for each term or literal for a given expression. This allows designers
to make use of fewer components, thus reducing the cost of a particular system.
It should be noted that there are no fixed rules that can be used to minimise a given expression. It is left
to an individuals ability to apply Boolean Theorems in order to minimise a function.
Example
Problems
1. Minimise the following functions using algebraic method:
Z = f(A,B,C) = + B + AB + AC
Z = f(A,B,C) = B + B + BC + A

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Karnaugh Maps
So far we can see that applying Boolean algebra can be awkward in order to simplify expressions. Apart
from being laborious (and requiring the remembering all the laws) the method can lead to solutions
which, though they appear minimal, are not.
The Karnaugh map provides a simple and straight-forward method of minimising boolean expressions.
With the Karnaugh map Boolean expressions having up to four and even six variables can be simplified.
So what is a Karnaugh map?
A Karnaugh map provides a pictorial method of grouping together expressions with common factors and
therefore eliminating unwanted variables. The Karnaugh map can also be described as a special
arrangement of a truth table.
The diagram below illustrates the correspondence between the Karnaugh map and the truth table
for the general case of a two variable problem.
The values inside the squares are copied from the output column of the truth table, therefore there is one
square in the map for every row in the truth table. Around the edge of the Karnaugh map are the values
of the two input variable. A is along the top and B is down the left hand side. The diagram below
explains this:
The values around the edge of the map can be thought of as coordinates. So as an example, the square on
the top right hand corner of the map in the above diagram has coordinates A=1 and B=0. This square
corresponds to the row in the truth table where A=1 and B=0 and F=1. Note that the value in the F
column represents a particular function to which the Karnaugh map corresponds.
Karnaugh Maps - Rules of Simplification
The Karnaugh map uses the following rules for the simplification of expressions by grouping together
adjacent cells containing ones

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• Groups may not include any cell containing a zero
• Groups may be horizontal or vertical, but not diagonal.
• Groups must contain 1, 2, 4, 8, or in general 2n
cells.
That is if n = 1, a group will contain two 1's since 21
= 2.
If n = 2, a group will contain four 1's since 22
= 4.
• Each group should be as large as possible.

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• Each cell containing a one must be in at least one group.
• Groups may overlap.
• Groups may wrap around the table. The leftmost cell in a row may be grouped with the
rightmost cell and the top cell in a column may be grouped with the bottom cell.
• There should be as few groups as possible, as long as this does not contradict any of the
previous rules.
Summmary:
1. No zeros allowed.

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2. No diagonals.
3. Only power of 2 number of cells in each group.
4. Groups should be as large as possible.
5. Every one must be in at least one group.
6. Overlapping allowed.
7. Wrap around allowed.
8. Fewest number of groups possible.
Example 1:
Consider the following map. The function plotted is: Z = f(A,B) = A + AB
• Note that values of the input variables form the rows and columns. That is the logic values of the
variables A and B (with one denoting true form and zero denoting false form) form the head of
the rows and columns respectively.
• Bear in mind that the above map is a one dimensional type which can be used to simplify an
expression in two variables.
• There is a two-dimensional map that can be used for up to four variables, and a three-
dimensional map for up to six variables.
Using algebraic simplification,
Z = A + AB
Z = A( + B)
Z = A
Variable B becomes redundant due to Boolean Theorem T9a.
Referring to the map above, the two adjacent 1's are grouped together. Through inspection it can
be seen that variable B has its true and false form within the group. This eliminates variable B
leaving only variable A which only has its true form. The minimised answer therefore is Z = A.
Example 2:
Consider the expression Z = f(A,B) = + A + B plotted on the Karnaugh map:
Pairs of 1's are grouped as shown above, and the simplified answer is obtained by using the following

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steps:
Note that two groups can be formed for the example given above, bearing in mind that the largest
rectangular clusters that can be made consist of two 1s. Notice that a 1 can belong to more than one
group.
The first group labelled I, consists of two 1s which correspond to A = 0, B = 0 and A = 1, B = 0. Put in
another way, all squares in this example that correspond to the area of the map where B = 0 contains 1s,
independent of the value of A. So when B = 0 the output is 1. The expression of the output will contain
the term
For group labelled II corresponds to the area of the map where A = 0. The group can therefore be
defined as . This implies that when A = 0 the output is 1. The output is therefore 1 whenever B = 0 and
A = 0
Hence the simplified answer is Z = +
Tabular Method of Minimisation
In order to understand the tabular method of minimisation, it is best you understand the numerical
assignment of Karnaugh map cells and the incompletely specified functions also known as the can't
happen conditions. This is because the tabular method is based on these principles.
The tabular method which is also known as the Quine-McCluskey method is particularly useful when
minimising functions having a large number of variables, e.g. The six-variable functions. Computer
programs have been developed employing this algorithm. The method reduces a function in standard
sum of products form to a set of prime implicants from which as many variables are eliminated as
possible. These prime implicants are then examined to see if some are redundant.
The tabular method makes repeated use of the law A + = 1. Note that Binary notation is used for the
function, although decimal notation is also used for the functions. As usual a variable in true form is
denoted by 1, in inverted form by 0, and the abscence of a variable by a dash ( - ).
Rules of Tabular Method
Consider a function of three variables f(A, B, C):
Consider the function:
Listing the two minterms shows they can be combined

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Now consider the following:
Note that these variables cannot be combined
This is because the FIRST RULE of the Tabular method for two terms to combine, and thus eliminate
one variable, is that they must differ in only one digit position.
Bear in mind that when two terms are combined, one of the combined terms has one digit more at logic
1 than the other combined term. This indicates that the number of 1's in a term is significant and is
referred to as its index.
For example: f(A, B, C, D)
0000...................Index 0
0010, 1000.............Index 1
1010, 0011, 1001.......Index 2
1110, 1011.............Index 3
1111...................Index 4
The necessary condition for combining two terms is that the indices of the two terms must differ by one
logic variable which must also be the same.
Example 1:
Consider the function: Z = f(A,B,C) = + C + A + A C
To make things easier, change the function into binary notation with index value and decimal value.
Tabulate the index groups in a colunm and insert the decimal value alongside.

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From the first list, we combine terms that differ by 1 digit only from one index group to the next. These
terms from the first list are then seperated into groups in the second list. Note that the ticks are just there
to show that one term has been combined with another term. From the second list we can see that the
expression is now reduced to: Z = + + C + A
From the second list note that the term having an index of 0 can be combined with the terms of index 1.
Bear in mind that the dash indicates a missing variable and must line up in order to get a third list. The
final simplified expression is: Z =
Bear in mind that any unticked terms in any list must be included in the final expression (none occured
here except from the last list). Note that the only prime implicant here is Z = .
The tabular method reduces the function to a set of prime implicants.
Note that the above solution can be derived algebracially. Attempt this in your notes.
Example 2:
Consider the function f(A, B, C, D) = (0,1,2,3,5,7,8,10,12,13,15), note that this is in decimal form.
(0000,0001,0010,0011,0101,0111,1000,1010,1100,1101,1111) in binary form.
(0,1,1,2,2,3,1,2,2,3,4) in the index form.
The prime implicants are: + + D + BD + A + AB
The chart is used to remove redundant prime implicants. A grid is prepared having all the prime
implicants listed at the left and all the minterms of the function along the top. Each minterm covered by
a given prime implicant is marked in the appropriate position.

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From the above chart, BD is an essential prime implicant. It is the only prime implicant that covers the
minterm decimal 15 and it also includes 5, 7 and 13. is also an essential prime implicant. It is the
only prime implicant that covers the minterm denoted by decimal 10 and it also includes the terms 0, 2
and 8. The other minterms of the function are 1, 3 and 12. Minterm 1 is present in and D. Similarly
for minterm 3. We can therefore use either of these prime implicants for these minterms. Minterm 12 is
present in A and AB , so again either can be used.
Thus, one minimal solution is: Z = + BD + + A
Adding Binary Numbers
A key requirement of digital computers is the ability to use logical functions to perform
arithmetic operations. The basis of this is addition; if we can add two binary numbers, we can
just as easily subtract them, or get a little fancier and perform multiplication and division.
How, then, do we add two binary numbers?
Let's start by adding two binary bits. Since each bit has only two possible values, 0 or 1,
there are only four possible combinations of inputs. These four possibilities, and the resulting
sums, are:
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 10
Whoops! That fourth line indicates that we have to account for two output bits when we
add two input bits: the sum and a possible carry. Let's set this up as a truth table with two
inputs and two outputs, and see where we can go from there.
INPUTS OUTPUTS
Well, this looks familiar, doesn't it? The Carry output is a
simple AND function, and the Sum is an Exclusive-OR.
Thus, we can use two gates to add these two bits together.
The resulting circuit is shown below.
A B CARRY SUM
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

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OK, we've got a good start on this circuit. However, we're not
done yet. In a computer, we'll have to add multi-bit numbers
together. If each pair of bits can produce an output carry, it must
also be able to recognize and include a carry from the next lower
order of magnitude. This is the same requirement as adding decimal
numbers -- if you have a carry from one column to the next, the next
column has to include that carry. We have to do the same thing with
binary numbers, for the same reason. As a result, the circuit to the
left is known as a "half adder," because it only does half of the job.
We need a circuit that will do the entire job.
To construct a full adder circuit, we'll need three inputs
and two outputs. Since we'll have both an input carry and an
output carry, we'll designate them as CIN and COUT. At the
same time, we'll use S to designate the final Sum output. The
resulting truth table is shown to the right. Hmmm. This is
looking a bit messy. It looks as if COUT may be either an
AND or an OR function, depending on the value of A, and S
is either an XOR or an XNOR, again depending on the value
of A. Looking a little more closely, however, we can note that
the S output is actually an XOR between the A input and the
half-adder SUM output with B and CIN inputs. Also, the
output carry will be true if any two or all three inputs are
logic 1. we can use two half-adder circuits. The first will add
A and B to produce a partial Sum, while the second will add
CIN to that Sum to produce the final S output. If either half-
adder produces a carry, there will be an output carry. Thus,
COUT will be an OR function of the half-adder Carry outputs.
The resulting full adder circuit is shown below.
INPUTS OUTPUTS
A B CIN COUT S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
The circuit above is really too complicated to be used in larger logic diagrams, so a
separate symbol, shown to the right, is used to represent a one-bit full adder. In fact, it is
common practice in logic diagrams to represent any complex function as a "black box" with
input and output signals designated. It is, after all, the logical function that is important, not
the exact method of performing that function.

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Now we can add two binary bits together, accounting for a possible carry from the next lower order of
magnitude, and sending a carry to the next higher order of magnitude. To perform multibit addition the
way a computer would, a full adder must be allocated for each bit to be added simultaneously. Thus, to
add two 4-bit numbers to produce a 4-bit sum (with a possible carry), you would need four full adders
with carry lines cascaded, as shown to the right. For two 8-bit numbers, you would need eight full
adders, which can be formed by cascading two of these 4-bit blocks. By extension, two binary numbers
of any size may be added in this manner.
Binary Subtraction
It is also quite possible to use this circuit for binary subtraction. If a negative number is applied to the B
inputs, the resulting sum will actually be the difference between the two numbers. We'll look at this
subject in more detail in the page on Negative Numbers and Binary Subtraction.
In a modern computer, the adder circuitry will include the means of negating one of the input numbers
directly, so the circuit can perform either addition or subtraction on demand. Other functions are
commonly included in modern implementations of the adder circuit, especially in modern
microprocessors.
We have seen how simple logic gates can perform the process of binary addition. It is only logical to
assume that a similar circuit could perform binary subtraction.
If we look at the possibilites involved in subtracting one 1-bit number from another, we can quickly see
that three of the four possible combinations are easy and straight-forward. The fourth one involves a bit
more:
0 - 0 = 0
1 - 0 = 1
1 - 1 = 0
0 - 1 = 1, with a borrow bit.

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That borrow bit is just like a borrow in decimal subtraction: it subtracts from the next higher order of
magnitude in the overall number. Let's see what the truth table looks like.
INPUTS OUTPUTS This is an interesting result. The difference, A-B, is still an Exclusive-OR
function, just as the sum was for addition. The borrow is still an AND
function, but is A'B instead of AB.
What we'd like to do, now, is find an easy way to use the binary adder to
perform subtraction as well. We already have half of it working: the
difference output. Can we simply invert the A input so the AND gate will
have the right signals? No, we can't, because that would invert the sense
of the Exclusive-OR function.
What would be really nice is to convert B to the negative equivalent of its
value, and then use the basic adder just as it stands. To see if we can do
that, let's consider negative binary numbers below.
A B
BORR
OW
A - B
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
A two-input multiplexer
One circuit I've received a number of requests for is the multiplexer circuit. This is a digital circuit with
multiple signal inputs, one of which is selected by separate address inputs to be sent to the single output.
It's not easy to describe without the logic diagram, but is easy to understand when the diagram is
available. A two-input multiplexer is shown below
The multiplexer circuit is typically used to combine two or
more digital signals onto a single line, by placing them there at
different times. Technically, this is known as time-division
multiplexing. Input A is the addressing input, which controls
which of the two data inputs, X0 or X1, will be transmitted to
the output. If the A input switches back and forth at a frequency
more than double the frequency of either digital signal, both
signals will be accurately reproduced, and can be separated
again by a demultiplexer circuit synchronized to the
multiplexer.The telephone network combines multiple audio
signals onto a single pair of wires using exactly this technique,
and is readily able to separate many telephone conversations so
that everyone's voice goes only to the intended recipient. With
the growth of the Internet and the World Wide Web, most
people have heard about T1 telephone lines. A T1 line can
transmit up to 24 individual telephone conversations by
multiplexing them in this manner.
A very common application for this type of circuit is found in computers, where dynamic memory uses
the same address lines for both row and column addressing. A set of multiplexers is used to first select
the row address to the memory, then switch to the column address. This scheme allows large amounts of
memory to be incorporated into the computer while limiting the number of copper traces required to
connect that memory to the rest of the computer circuitry. In such an application, this circuit is
commonly called a data selector.

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Decoder/Demultiplexer
The opposite of the multiplexer circuit, logically enough, is the demultiplexer. This circuit takes a single
data input and one or more address inputs, and selects which of multiple outputs will receive the input
signal. The same circuit can also be used as a decoder, by using the address inputs as a binary number
and producing an output signal on the single output that matches the binary address input. In this
application, the data input line functions as a circuit enabler — if the circuit is disabled, no output will
show activity regardless of the binary input number.
A one-line to two-line decoder/demultiplexer is shown below.
This circuit uses the same AND gates and the same addressing scheme as the two-
input multiplexer circuit shown in these pages. The basic difference is that it is the
inputs that are combined and the outputs that are separate. By making this change,
we get a circuit that is the inverse of the two-input multiplexer. If you were to
construct both circuits on a single breadboard, connect the multiplexer output to
the data IN of the demultiplexer, and drive the (A)ddress inputs of both circuits
with the same signal, you would find that the initial X0 input would be
transmitted to OUT0 and the X1 input would reach only OUT1.
The one problem with this arrangement is that one of the two outputs will be
inactive while the other is active. To retain the output signal, we need to add a
latch circuit that can follow the data signal while it's active, but will hold the last
signal state while the other data signal is active. An excellent circuit for this is the
D (or Data) Latch. By placing a latch after each output and using the Addressing
input (or its inverse) to control them, we can maintain both output signals at all
times. If the Address input changes much more rapidly than the data inputs, the
output signals will match the inputs faithfully.
Like multiplexers, demultiplexers are not limited to two data signals. If we use two addressing inputs,
we can demultiplex up to four data signals. With three addressing inputs, we can demultiplex eight
signals. The demonstration of the 2-to-4 line decoder/demultiplexer is much smaller than the demo for
the four-input multiplexer, because it has fewer independent input signals. With one data input and two
addressing inputs, the decoder/demultiplexer only needs 8 images for the full demonstration.
Sequential Logic:
In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the
present input but also on the history of the input. This is in contrast to combinational logic, whose output
is a function of, and only of, the present input. In other words, sequential logic has storage (memory)
while combinational logic does not.
Sequential logic is therefore used to construct some types of computer memory, other types of delay and
storage elements, and finite state machines. Most practical computer circuits are a mixture of
combinational and sequential logic.
There are two types of finite state machine that can be built from sequential logic circuits:
• Moore machine: the output depends only on the internal state. (Since the internal state only
changes on a clock edge, the output only changes on a clock edge too).

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• Mealy machine: the output depends not only on the internal state, but also on the inputs.
Nearly all sequential logic today is 'clocked' or 'synchronous logic' logic: there is a 'clock' signal, and all
internal memory (the 'internal state') changes only on a clock edge. The basic storage element in
sequential logic is the flip-flop.
The main advantage of synchronous logic is its simplicity. Every operation in the circuit must be
completed inside a fixed interval of time between two clock pulses, called a 'clock cycle'. As long as this
condition is met (ignoring certain other details), the circuit is guaranteed to be reliable. Synchronous
logic also has two main disadvantages, as follows.
1. The clock signal must be distributed to every flip-flop in the circuit. As the clock is usually a high-
frequency signal, this distribution consumes a relatively large amount of power and dissipates much
heat. Even the flip-flops that are doing nothing consume a small amount of power, thereby generating
waste heat in the chip.
2. The maximum possible clock rate is determined by the slowest logic path in the circuit, otherwise
known as the critical path. This means that every logical calculation, from the simplest to the most
complex, must complete in one clock cycle. One way around this limitation is to split complex
operations into several simple operations, a technique known as 'pipelining'. This technique is prominent
within microprocessor design, and helps to improve the clock rate of modern processors.
Flip-Flops
The memory elements in a sequential circuit are called flip-flops. A flip-flop circuit has two outputs, one
for the normal value and one for the complement value of the stored bit. Binary information can enter a
flip-flop in a variety of ways and gives rise to different types of flip-flops.
Introduction - Basic Flip-Flop Circuit
A flip-flop circuit can be constructed from two NAND gates or two NOR gates. These flip-flops are
shown in Figure 2 and Figure 3. Each flip-flop has two outputs, Q and Q', and two inputs, set and reset.
This type of flip-flop is referred to as an SR flip-flop or SR latch. The flip-flop in Figure 2 has two useful
states. When Q=1 and Q'=0, it is in the set state (or 1-state). When Q=0 and Q'=1, it is in the clear state
(or 0-state). The outputs Q and Q' are complements of each other and are referred to as the normal and
complement outputs, respectively. The binary state of the flip-flop is taken to be the value of the normal
output.
When a 1 is applied to both the set and reset inputs of the flip-flop in Figure 2, both Q and Q' outputs go
to 0. This condition violates the fact that both outputs are complements of each other. In normal
operation this condition must be avoided by making sure that 1's are not applied to both inputs
simultaneously.

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(a) Logic diagram
Figure 2. Basic flip-flop circuit with NOR gates
(b) Truth table
Figure 3. Basic flip-flop circuit with NAND gates
(a) Logic diagram
(b) Truth table
The NAND basic flip-flop circuit in Figure 3(a) operates with inputs normally at 1 unless the state of the
flip-flop has to be changed. A 0 applied momentarily to the set input causes Q to go to 1 and Q' to go to
0, putting the flip-flop in the set state. When both inputs go to 0, both outputs go to 1. This condition
should be avoided in normal operation.
Introduction - Clocked SR Flip-Flop
The clocked SR flip-flop shown in Figure 4 consists of a basic NOR flip-flop and two AND gates. The
outputs of the two AND gates remain at 0 as long as the clock pulse (or CP) is 0, regardless of the S and
R input values. When the clock pulse goes to 1, information from the S and R inputs passes through to
the basic flip-flop. With both S=1 and R=1, the occurrence of a clock pulse causes both outputs to
momentarily go to 0. When the pulse is removed, the state of the flip-flop is indeterminate, ie., either
state may result, depending on whether the set or reset input of the flip-flop remains a 1 longer than the
transition to 0 at the end of the pulse.
(a) Logic diagram (b) Truth table
Figure 4. Clocked SR flip-flop
Introduction - D Flip-Flop
The D flip-flop shown in Figure 5 is a modification of the clocked SR flip-flop. The D input goes
directly into the S input and the complement of the D input goes to the R input. The D input is sampled
during the occurrence of a clock pulse. If it is 1, the flip-flop is switched to the set state (unless it was
already set). If it is 0, the flip-flop switches to the clear state.

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(a) Logic diagram with NAND gates (b) Graphical symbol (c) Transition table
Figure 5. Clocked D flip-flop
Introduction - JK Flip-Flop
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined
in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop (note that in a JK
flip-flop, the letter J is for set and the letter K is for clear). When logic 1 inputs are applied to both J and
K simultaneously, the flip-flop switches to its complement state, ie., if Q=1, it switches to Q=0 and vice
versa.
A clocked JK flip-flop is shown in Figure 6. Output Q is ANDed with K and CP inputs so that the flip-
flop is cleared during a clock pulse only if Q was previously 1. Similarly, ouput Q' is ANDed with J and
CP inputs so that the flip-flop is set with a clock pulse only if Q' was previously 1.
Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1 (while
J=K=1) after the outputs have been complemented once will cause repeated and continuous transitions
of the outputs. To avoid this, the clock pulses must have a time duration less than the propagation delay
through the flip-flop. The restriction on the pulse width can be eliminated with a master-slave or edge-
triggered construction. The same reasoning also applies to the T flip-flop presented next.
(a) Logic diagram (b) Graphical symbol (c) Transition table
Figure 6. Clocked JK flip-flop
Introduction - T Flip-Flop
The T flip-flop is a single input version of the JK flip-flop. As shown in Figure 7, the T flip-flop is
obtained from the JK type if both inputs are tied together. The output of the T flip-flop "toggles" with
each clock pulse.

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(a) Logic diagram (b) Graphical symbol (c) Transition table
Figure 7. Clocked T flip-flop
Introduction - Triggering of Flip-flops
The state of a flip-flop is changed by a momentary change in the input signal. This change is called a
trigger and the transition it causes is said to trigger the flip-flop. The basic circuits of Figure 2 and
Figure 3 require an input trigger defined by a change in signal level. This level must be returned to its
initial level before a second trigger is applied. Clocked flip-flops are triggered by pulses.
The feedback path between the combinational circuit and memory elements in Figure 1 can produce
instability if the outputs of the memory elements (flip-flops) are changing while the outputs of the
combinational circuit that go to the flip-flop inputs are being sampled by the clock pulse. A way to solve
the feedback timing problem is to make the flip-flop sensitive to the pulse transition rather than the pulse
duration.
The clock pulse goes through two signal transitions: from 0 to 1 and the return from 1 to 0. As shown in
Figure 8 the positive transition is defined as the positive edge and the negative transition as the negative
edge.
Figure 8. Definition of clock pulse transition
The clocked flip-flops already introduced are triggered during the positive edge of the pulse, and the
state transition starts as soon as the pulse reaches the logic-1 level. If the other inputs change while the
clock is still 1, a new output state may occur. If the flip-flop is made to respond to the positive (or
negative) edge transition only, instead of the entire pulse duration, then the multiple-transition problem
can be eliminated.
Introduction - Master-Slave Flip-Flop
A master-slave flip-flop is constructed from two seperate flip-flops. One circuit serves as a master and
the other as a slave. The logic diagram of an SR flip-flop is shown in Figure 9. The master flip-flop is
enabled on the positive edge of the clock pulse CP and the slave flip-flop is disabled by the inverter. The
information at the external R and S inputs is transmitted to the master flip-flop. When the pulse returns

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to 0, the master flip-flop is disabled and the slave flip-flop is enabled. The slave flip-flop then goes to
the same state as the master flip-flop.
Figure 9. Logic diagram of a master-slave flip-flop
The timing relationship is shown in Figure 10 and is assumed that the flip-flop is in the clear state prior
to the occurrence of the clock pulse. The output state of the master-slave flip-flop occurs on the negative
transition of the clock pulse. Some master-slave flip-flops change output state on the positive transition
of the clock pulse by having an additional inverter between the CP terminal and the input of the master.
Figure 10. Timing relationship in a master slave flip-flop
Introduction - Edge Triggered Flip-Flop
Another type of flip-flop that synchronizes the state changes during a clock pulse transition is the edge-
triggered flip-flop. When the clock pulse input exceeds a specific threshold level, the inputs are locked
out and the flip-flop is not affected by further changes in the inputs until the clock pulse returns to 0 and
another pulse occurs. Some edge-triggered flip-flops cause a transition on the positive edge of the clock
pulse (positive-edge-triggered), and others on the negative edge of the pulse (negative-edge-triggered).
The logic diagram of a D-type positive-edge-triggered flip-flop is shown in Figure 11.
Figure 11. D-type positive-edge triggered flip-flop

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When using different types of flip-flops in the same circuit, one must ensure that all flip-flop outputs
make their transitions at the same time, ie., during either the negative edge or the positive edge of the
clock pulse.
Introduction - Direct Inputs
Flip-flops in IC packages sometimes provide special inputs for setting or clearing the flip-flop
asynchronously. They are usually called preset and clear. They affect the flip-flop without the need for a
clock pulse. These inputs are useful for bringing flip-flops to an intial state before their clocked
operation. For example, after power is turned on in a digital system, the states of the flip-flops are
indeterminate. Activating the clear input clears all the flip-flops to an initial state of 0. The graphic
symbol of a JK flip-flop with an active-low clear is shown in Figure.
(a) Graphic Symbol (b) Transition table
JK flip-flop with direct clear
Memory Devices
Introduction
Memory is memory is memory, right? Well, not exactly. There are many different flavors of memory
available for embedded systems.
The various types of memory.

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Random Access Memory
This type of memory is the kind most of us probably think of when talking about how much memory is
available. Random access memory (RAM) is the kind of memory used to hold programs and data when
a processor is active. Specifying the correct row (RAS) and column (CAS) of the memory block you
wish to access can access any block of data stored in the RAM chip. Generally programmers don't like
to think about and calculate the rows and columns needed to access a bit of data, so most
microprocessors have special support chips that convert a flat memory address into the correct row and
columns needed to read data from RAM. That way as a programmer, you just specify an address as a
number and the memory chips convert that into the proper row and column values to access the correct
block of RAM. RAM is packaged as a chip, or perhaps as a series of chips on a small board called a
module. Sizes vary from 4K RAM chips, up to 128MB RAM modules, or even larger. All embedded
systems need at least a small amount of RAM to operate correctly.
Different types of RAM.
Dynamic RAM
This kind of RAM is the most commonly used kind of RAM due to its low cost. Basically Dynamic
RAM consists of a capacitor and a transistor. The capacitor can either be charged (bit = 1) or discharged
(bit = 0). The transistor is used to either read the current capacitor state, or changes the state to charged
(1) or discharged (0). Dynamic RAM has one serious drawback however. Whenever you store a bit of
information in a Dynamic RAM location, that information is slowly lost. This is because a capacitor is
not a perfect storage device. It tends to leak a bit over time and slowly loses its charge. This means that
to keep the information current, before the information has been totally lost, the CPU must read and
rewrite the information. This is known as a memory refresh. Typically this must be down every few
milliseconds. Most microprocessors on the market are built to work with Dynamic RAM and have
special pins and an internal timer. The microprocessor uses those special pins to periodically stop
whatever it is doing, so it can refresh the Dynamic RAM's memory. Older processors forced the
programmer to create a memory refresh function, but newer processors do this for us automatically.
There is one other very important factor to understand about Dynamic RAM. That is the speed at which
memory can be read, or written, to the RAM. This is called the access time. It determines just how much
time must elapse between attempts to access data from the same RAM chip. Generally this is specified
in nanoseconds, but some RAM may be slow enough to be specified in microseconds. When the
processor is operating faster than the RAM access time, it is necessary to slow down the CPU by
inserting wait states into the system. Basically this means the CPU may have to do nothing for a few
nanoseconds or microseconds, until the RAM is ready to be accessed again.
Access Time Example -
Assume that the CPU is operating with a clock of 20 MHz. This means that the
processor itself can theoretically execute 1 step or instruction every 0.00000005
seconds, or 50 nanoseconds. In order to run at full speed with no wait states, the

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Dynamic RAM used must have an access time of 50 nanoseconds or less. By using
two Dynamic RAM chips, arranged so first one chip, then the other is accessed,
engineers can reduce cost by using slower 100 nanosecond memory.
It is still possible however that the program may need to access memory from the same chip in less than
100 nanoseconds. In this case, the processor is required to wait until the RAM chip is ready for access.
Most modern processors have a WAIT pin which is used for just this purpose. Basically the RAM chip
asserts the WAIT line whenever it is not ready. The WAIT line is then connected to the CPU, only when
that RAM chip is being accessed. When the CPU detects that the WAIT line is active, it will pause until
the WAIT line indicates it is now safe to again access the RAM.
Static RAM
With Static RAM, a flip-flop is used to create a memory cell. A flip-flop is a series of 4 transistors
interconnected in such a way that circuit is either on (1) or off (0). Since this is an active circuit made up
from transistors, the memory never needs to be refreshed. Unfortunately, the extra transistors needed to
make Static RAM chips means it takes up more space, which in turns makes it more expensive.
Therefore Static RAM is generally reserved for use only when absolutely necessary, such as for storing
your computer's BIOS settings, or for acting as a local cache buffer between the CPU and the rest of
Dynamic RAM.
FPM DRAM
Fast-page mode Dynamic RAM is the original type DRAM that was widely used. This kind of RAM
that has to wait through the entire process of decoding an address and reading or writing the bit of data
before it can move on to the next bit.
EDO DRAM
Extended Data-Out Dynamic RAM is a new type of DRAM that has become popular. The chief
advantage of EDO DRAM is that it can begin decoding the next bit's address before it has completed
reading the bit from the previous address. This makes it generally about 5-10% faster than normal FPM
DRAM.
SDRAM
Synchronous Dynamic RAM is a special kind of EDO RAM. It operates in a burst mode, by assuming
that most memory accesses are done sequentially. Therefore, it decodes the row address first, then steps
through all the column addresses, reading bits, without recalculating the row address over and over
again. This type of RAM is about 5-10% faster than EDO RAM. It is the most widely used type of RAM
in modern computer systems.
RDRAM
Rambus Dynamic RAM departs from the traditional Dynamic RAM methods of accessing memory
based on a row and column. Instead it uses a special high-speed bus to read and write to memory in
parallel mode. This allows it to achieve even faster access times than SDRAM, but does cost extra. In
addition, special Rambus interface chips are needed to act as a translator between the processor and the
RAM. A few of the new processors on the market include Rambus support on the CPU chip itself. This

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kind of RAM is expected to dominate the personal computer industry over the next several years, due to
its very high speeds (up to 1.6GB per second transfer rates). Currently it is generally only available on
high cost servers where performance is more important than costs.
PCMCIA Memory Cards
This is a special kind of memory widely used on notebook and laptop computers. It is DRAM with extra
support circuitry that allows it to plugged into a computer's PCMCIA slot to add RAM to the computer
system.
Flash RAM
This is a term for a type of DRAM that has built-in memory refresh circuitry. It is used by many
different computer systems, including embedded systems. This kind of RAM keeps its memory active
by continuously applying a same voltage to the RAM chips, even when the power is off. This is the type
of memory used to keep the time in a VCR, and stores your favorite stations on the radio in your car,
and keeps your BIOS settings for you computer. If the power is ever completely lost, so is the memory
held in Flash RAM. This is why VCRs tend to flash 12:00 after a power outage. This is also why your
computer loses its hard drive and other BIOS settings, should the backup battery on the motherboard
ever fail.
VRAM
Video RAM is a special type of DRAM that allows two processors to access the same memory
simultaneously. It is very useful for video cards, where the main system processor may be writing to
video RAM, while at the same time the processor is reading the memory in order to update the video
display. The main processor generally accesses memory randomly, while the video processor accesses
the memory serially, or sequentially. Very often 3-D accelerated graphics cards use this kind of memory
to achieve very high-speed operations. Basically the main processor never has to wait to access memory
while the video processor is reading it.
Read-Only Memory
The next type of memory is known as Read-Only Memory (ROM). Basically ROM chips can be read
from, but never written to. They are used to hold programs that never change on the computer. For
example, a personal computer's BIOS code is almost always stored in one or more ROM chips on the
motherboard. When the processor is reset, it jumps to a fixed memory location, where it begins to
execute the instructions found there. Refer to the processor's programming card or other reference
material to determine the memory address the CPU jumps to. Like RAM chips, ROM chips are available
in a variety of sizes and bit widths.
ROM
A ROM chip is programmed when manufactured. In order to purchase ROM chips with your own code
on them, you must contact a manufacturer and send them the exact information you wish them to encode
onto the chip. The chips themselves are fairly cheap, but must be purchased in large quantities; since the
setup needed to mass-produce the ROM chips is often times more expensive than the chip itself. These
mass-produced ROM chips are usually called masked ROMs.

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PROM
This is a special form of ROM that chip manufacturers use to create ROM chips. A PROM chip can
have code installed exactly one time. Generally when getting a chip manufacturer to build custom ROM
chips, they will use a generic PROM chip and download the information to it in a large production run.
There are many PROM burners, or PROM programmers, available on the market for building ROM
chips to be used for testing and design purposes.
EPROM
This special kind of ROM chip can be erased by exposing a small window on the chip to ultraviolet
light, which clears the contents of the EPROM. It takes about 2 weeks of sitting in a brightly lit kitchen
window to erase an EPROM. Special lights are available which can reduce the time it takes to erase the
EPROM. Once the EPROM is erased, it can be reprogrammed again using a PROM burner. This was a
great improvement over PROM chips, since a small mistake in the downloaded code stored on the chip
does not mean you have to throw the chip away. Instead, you can erase it and try again.
EEPROM
This is also an erasable kind of ROM. It is sometimes called a Flash ROM chip. In this case, erasing the
ROM is accomplished electronically instead of using ultraviolet light. Many newer computer systems
use this kind of memory to hold the BIOS code. This way, it is possible to download a new set of BIOS
instructions to the ROM chip by running a special program on the computer. Many of the PROM
burners on the market today can handle a variety of PROM's, EPROM's, and EEPROM's.
Other Memory Devices
There are several other kinds of memory devices available for use with both general-purpose and
embedded computer systems. They include floppy disks, hard drives, CD-ROM disks and many others.
When using these types of devices however, an additional embedded controller generally handles the
communication between the main processor and the hardware device. Of course, this is a kind of
embedded programming, but is an area that we will only briefly discuss, since many embedded
controllers already have this kind of support built-in, or included on the main board of the system.
Memory card
A memory card or flash memory card is a solid-state electronic flash memory data storage device
used with digital cameras, handheld and Mobile computers, telephones, music players, video game
consoles, and other electronics. They offer high re-record-ability, power-free storage, small form factor,
and rugged environmental specifications. There are also non-solid-state memory cards that do not use
flash memory, and there are different types of flash memory.

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There are many different types of memory cards and jobs they are used for. Some common places
include in digital cameras, game consoles, cell phones, and industrial applications. PC card (PCMCIA)
were among first commercial memory card formats (type I cards) to come out in the 1990s, but are now
only mainly used in industrial applications and for I/O jobs (using types I/II/III), as a connection
standard for devices (such as a modem). Also in 1990s, a number of memory card formats smaller than
PC Card came out, including CompactFlash, SmartMedia, and Miniature Card. In other areas, tiny
embedded memory cards (SID) were used in cell phones, game consoles started using proprietary
memory card formats, and devices like PDAs and digital music players started using removable memory
cards.
From the late 1990s into the early 2000s a host of new formats appeared, including SD/MMC, Memory
Stick, xD-Picture Card, and a number of variants and smaller cards. The desire for ultra-small cards for
cell-phones, PDAs, and compact digital cameras drove a trend toward smaller cards that left the
previous generation of "compact" cards looking big. In digital cameras SmartMedia and CompactFlash
had been very successful, in 2001 SM alone captured 50% of the digital camera market and CF had a
strangle hold on professional digital cameras. By 2005 however, SD/MMC had nearly taken over
SmartMedia's spot, though not to the same level and with stiff competition coming from Memory Stick
variants, xD, as well as CompactFlash. In industrial fields, even the venerable PC card (PCMCIA)
memory cards still manage to maintain a niche, while in cell-phones and PDAs, the memory card market
is highly fragmented. Nowadays, most new PCs have built-in slots for a variety of memory cards;
Memory Stick, CompactFlash, SD, etc. Some digital gadgets support more than one memory card to
ensure compatibility.
Data table of selected memory card formats
Name Acronym Form factor DRM
PC Card PCMCIA 85.6 × 54 × 3.3 mm None
CompactFlash I CF-I 43 × 36 × 3.3 mm None
CompactFlash II CF-II 43 × 36 × 5.5 mm None
SmartMedia SM / SMC 45 × 37 × 0.76 mm None
Memory Stick MS 50.0 × 21.5 × 2.8 mm MagicGate
Memory Stick Duo MSD 31.0 × 20.0 × 1.6 mm MagicGate
Memory Stick PRO Duo MSPD 31.0 × 20.0 × 1.6 mm MagicGate
Memory Stick PRO-HG Duo MSPDX 31.0 × 20.0 × 1.6 mm MagicGate
Memory Stick Micro M2 M2 15.0 × 12.5 × 1.2 mm MagicGate
Multimedia Card MMC 32 × 24 × 1.5 mm None
Reduced Size Multimedia Card RS-MMC 16 × 24 × 1.5 mm None
MMCmicro Card MMCmicro 12 × 14 × 1.1 mm None
Secure Digital card SD 32 × 24 × 2.1 mm CPRM
SxS SxS
Universal Flash Storage UFS
miniSD card miniSD 21.5 × 20 × 1.4 mm CPRM
microSD card microSD 11 × 15 × 0.7 mm CPRM

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xD-Picture Card xD 20 × 25 × 1.7 mm None
Intelligent Stick iStick 24 x 18 x 2.8 mm None
Serial Flash Module SFM 45 x 15 mm None
µ card µcard 32 x 24 x 1 mm Unknown
NT Card NT NT+ 44 x 24 x 2.5 mm None
Since many EEPROM devices only allow a limited number of write cycles, some of these cards
incorporate wear levelling algorithms to spread the wear and to avoid wearing out specific places which
are often written to.
Programmable Logic Devices
In the world of digital electronic systems, there are three basic kinds of devices:
Memory devices : store random information (such as the contents of a spreadsheet or database)
microprocessors,: execute software instructions to perform a wide variety of tasks (such as running a
word processing program or video game)
Logic devices : provide specific functions,( including device-to-device interfacing, data communication,
signal processing, data display, timing and control operations, and almost every other function a system
must perform.)
Logic devices can be classified into two categories - fixed and programmable.
the circuits in a fixed logic device are permanent, they perform one function or set of functions - once
manufactured, they cannot be changed.
A PLD is an electronic component used to build digital circuits. programmable logic devices (PLDs) can
be changed at any time to perform any number of functions.
Advantages of PLD
PLDs offer a number of important advantages over fixed logic devices, including:
PLDs offer customers much more flexibility during the design cycle because design iterations are
simple, and the results of design changes can be seen immediately in working parts.
PLDs do not require long lead times for prototypes or production parts - the PLDs are already on a
distributor's shelf and ready for shipment.
PLDs do not require customers to pay for large costs and purchase expensive mask sets.
PLDs allow customers to order just the number of parts they need, when they need them, allowing them
to control inventory.
PLDs can be reprogrammed even after a piece of equipment is shipped to a customer.
In fact, thanks to programmable logic devices, a number of equipment manufacturers now tout the
ability to add new features or upgrade products that already are in the field. To do this, they simply
upload a new programming file to the PLD, via the Internet, creating new hardware logic in the system.

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PLDs and ROMs
Before PLDs were invented, read-only memory (ROM) chips were used to create arbitrary
combinatorial logic functions of a number of inputs. Disadvantages of ROM memories:
they are usually much slower than PLD circuits,
they cannot necessarily provide safe "covers" for asynchronous logic transitions,
they consume more power, and
because only a small fraction of their capacity is used in any one application, they often make an
inefficient use of space.
Benefits of PLD:
With programmable logic devices, designers use inexpensive software tools to quickly develop,
simulate, and test their designs. Then, a design can be quickly programmed into a device, and
immediately tested in a live circuit. The PLD can be used in a network router, a DSL modem, a DVD
player, or an automotive navigation system.
Another benefit of using PLDs is that during the design phase customers can change the circuitry as
often as they want until the design operates to their satisfaction. That's because PLDs are based on re-
writable memory technology - to change the design, the device is simply reprogrammed.
Programmable Logic Devices
Pre-fabricated building block of many AND/OR gates (or NOR, NAND)
"Personalized" by making or breaking connections among the gates
Basic Programmable Logic Organizations
Depending on which of the AND/OR logic arrays is programmable, we have three basic organizations
PLD

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Programmable Logic Devices (PLDs)
• Several different "architectures" available – We will focus only on PAL and CPLD
• PALs (Programmable Array Logic) and CPLDs (Complex Programmable Logic Device) are examples
of PLDs
PAL devices consisted of a small PROM (programmable read-only memory) core and additional output
logic used to implement particular desired logic functions with few components.
• PAL:
– implement SOP expressions in canonical form
– made from a Programmable AND section and
a Fixed OR section
– typically can implement 8 product terms
– programmed like PROMs using fuses
– one-time programmable
• PLAs:
– Devices with programmable AND and programmable OR
• CPLDs:
– re-programmed like EEPROMs
– Electrically erasable
PALs and PLAs
PALs and PLAs
Of the two organizations the PLA is the most flexible
•One PLA can implement a huge range of logic functions
•But many pins; large package, higher cost
For PALs :
•Many device variations needed
•Each device is cheaper than a PLA
•the programmable elements (fuses) connect to the AND gates. These AND gates, also known as
product terms, are ORed together to form a sum-of-products logic array.

Digital logic
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Some PLD programming languages:
for low-complexity devices; PALASM and ABEL,
for high-comlexity; Verilog and VHDL
PAL
PLA
A programmable logic array (PLA) is a programmable device used to implement combinational logic
circuits. The PLA has a set of programmable AND logic, which link to a set of programmable OR logic,
which can then be conditionally complemented to produce an output. This layout allows for a large
number of logic functions to be synthesized in the sum of products (and sometimes product of sums)
canonical forms
One application of a PLA is to implement the control over a datapath. It defines various states in an
instruction set, and produces the next state (by conditional branching). Programmable Logic Arrays
should correspond to a state diagram for the system.
Other commonly used programmable logic devices are PAL, CPLD and FPGA.
PLA Logic Implementation
Complex Programmable Logic Devices
Complex PLDs typically combine PAL combinational logic with FFs
•Organized into logic blocks
•Fixed OR array size
•Combinational or registered output
•Some pins are inputs only
Usually enough logic for simple counters, state machines, decoders, etc.
PALs are available only in small sizes, equivalent to a few hundred logic gates. For bigger logic circuits,
CPLDs can be used. CPLDs can replace thousands, or even hundreds of thousands, of logic gates.
CPLDs are programmed using a printed circuit board, then feed it with a serial data stream from a
personal computer.
FGPA
FPGAs offer the highest amount of logic density, the most features, and the highest performance. The
largest FPGA (now shipping, part of the Xilinx Virtex™ line of devices), provides eight million "system
gates".
These advanced devices also offer features such as built-in hardwired processors (such as the IBM
Power PC), substantial amounts of memory, clock management systems, and support for many of the
latest, very fast device-to-device signaling technologies.
FPGAs are used in a wide variety of applications ranging from data processing and storage, to
instrumentation, telecommunications, and digital signal processing.

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CPLDs, by contrast, offer much smaller amounts of logic - up to about 10,000 gates. But CPLDs offer
very predictable timing characteristics and are therefore ideal for critical control applications.
CPLDs such as the Xilinx CoolRunner™ series also require extremely low amounts of power and are
very inexpensive, making them ideal for cost-sensitive, battery-operated, portable applications such as
mobile phones and digital handheld assistants.
Field Programmalble Gate Arrays (FPGAs)
FPGAs have much more logic than CPLDs
•2K to 400K equivalent gates
•Requires different architecture
•FPGAs can be RAM-based or Flash-based
•RAM FPGAs must be programmed at power-on
•External memory needed for programming data
•May be dynamically reconfigured
•Flash FPGAs store program data in non-volitile memory
•Reprogramming is more difficult
•Holds configuration when power is off
FPGA Structure
Typical organization in 2-D array
•Configurable logic blocks (CLBs) contain functional logic
•Combinational functions plus FFs
•Complexity varies by device
•CLB interconnect is either local or long line
•CLBs have connections to local neighbors
•Horizontal and vertical channels use for long distance
•Channel intersections have switch matrix
•IOBs (I/O logic Blocks) connect to pins
•Usually have some additional C.L./FF in block
Differences between FGPA and CPLD
Features in common with CPLD:
Non-volatile configuration memory. Unlike many FPGAs, an external configuration ROM isn't
required, and the CPLD can function immediately on system start-up.
For all but the largest devices, routing constrains most logic blocks to have input and output signals
connected to external pins (little opportunity for internal state storage or deeply layered logic).
Features in common with FPGAs:
Large number of gates available. CPLDs typically have the equivalent of thousands to tens of
thousands of logic gates, allowing implementation of moderately complicated data processing devices.
PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of
thousands to several million.
Some provisions for logic more flexible than sum-of-product expressions, including complicated
feedback paths between macro cells, and specialized logic for implementing various commonly-used
functions (such as integer arithmetic).
The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-
volatile memory in the CPLD. The differences in architectural approach become more apparent farther
from this intermediate region.
Programmable Logic Controller (PLC)

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PLCs are the control hubs for a wide variety of automated systems and processes.
A PLC, is a microprocessor used for automation of industrial processes, such as control of machinery on
factory assembly lines. Unlike general-purpose computers, the PLC can be designed for
extended temperature ranges,
dirty or dusty conditions,
immunity to electrical noise,
resistance to vibration and impact.
relay control, motion control, process control, distributed control systems and networking. PLCs
operate electric motors, pneumatic or hydraulic cylinders or diaphragms,
Programs to control machine operation are stored in battery-backed or read-only memory.
A PLC is an example of a real time system since output results must be produced in response to input
conditions within a strictly bounded time.
The data handling, storage, processing power and communication capabilities of some modern PLCs are
approximately equivalent to desktop computers. The main difference from other computers are the
special input/output arrangements. These connect the PLC to sensors and actuators. PLCs read limit
switches, temperature indicators and the positions of complex positioning systems. Some even use
machine vision.

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