The following Verilog always block implements a behavioral model of a D flip-flop:
reg Q;
always @(posedge clock)
begin
Q = D;
end
Recall the characteristic equation for a J-K flip-flop is Q+ = JQ' + K'Q.
Modify the Verilog code in this always block to model a J-K flip-flop.
Solution
reg Q;
always @(posedge clock)
begin
Q = ((~J)&Q)|(K&(~Q));
end