3. ARCHITECTURE OF 8085 MICROPROCESSOR
• Architecture is defined as ‘internal logic design of microprocessor, which
determine how and what various operations are done by
"MICROPROCESSOR".
• The microprocessor is programmable logic device designed with internal
register, flip-flop and timing control elements.
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 3
5. BLOCKS IN 8085
• ALU
• Registers
• Instruction Register and Instruction Decoder
• Timing and Control unit
• Serial I/O Control
• Interrupt control
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 5
7. BUS (ADDRESS BUS, DATA BUS & CONTROL BUS)
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 7
8. ADDRESS BUS
• Address bus of 8085 Microprocessor is a group of 16 lines, identified as A0 – A15.
• This bus is unidirectional (Data flow in one direction) from Microprocessor to peripheral
devices.
• Each memory location in 64 Kbyte memory (216 =65536=64K) or peripheral I/O identified
with 16 bit binary number (0000H – FFFFH) called address.
DATA BUS
• Data bus is a group of 8 lines used for data flow between microprocessor and I/O device,
these lines are bidirectional lines from (00 – FF) =28 =256 numbers. 8085 Microprocessor is
called 8 bit Microprocessor which consist of 8 bit Data bus that can be denote as D0-D7.
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 8
9. 0 7
AD0 – AD7
PIN 19-12
(BIDIRECTIONAL)
These pins serve the dual purpose of
transmitting lower order address and
data byte.
During 1st clock cycle, these pins act as
lower half of address.
In remaining clock cycles, these pins
act as data bus.
The separation of lower order address
and data is done by address latch.
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 9
10. 8 15
A8 –A15 PIN 21-28
(UNIDIRECTIONAL)
These pins carry the higher order
of address bus.
The address is sent from
microprocessor to memory.
These 8 pins are switched to high
impedance state during HOLD and
RESET mode.
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 10
11. ALU (ARITHMETIC AND LOGIC UNIT)
ALU
• 20 arithmetic operations (Like ADD, SUB,
Compare, Increment, Decrement, Complement
etc)
• 14 logical operations (Like AND, OR, NAND,
NOR, EX-OR, left/ right shift etc)
• Consist of accumulator, temporary register,
arithmetic and logical circuits and five flags.
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 11
12. ALU (ARITHMETIC AND LOGIC UNIT)
A REG
• used to store 8-bit input data and to
execute arithmetic and logical operations.
• The result of arithmetic and logical
operation is stored in the accumulator.
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 12
13. ALU (ARITHMETIC AND LOGIC UNIT)
TEMPORARY REGISTER
• It is utilized to hold the data temporary
during the arithmetic and logical
operations.
• 8 bit register
• Data transfer from reg (B,C,D,E,H,L) or
Memory Location ( Immediate address
ADI 05H or Direct address LDA 4500H)
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 13
14. FLAGS
• S (Sign) flag − After arithmetic instruction execution if D7 bit is 1, the sign flag is set. It is used for signed
numbers. If D7 is 1 means negative number. If D7 is 0 means positive number.
• Z (Zero) flag − The zero flag is set if ALU operation result is 0.
• AC (Auxiliary Carry) flag − In arithmetic operation, when carry is generated by digit D3 and passed on
to digit D4, the AC flag is set. (01+0F=00010000 , ACY=1)
• P (Parity) flag − After arithmetic or logic operation, if result has even number of 1s, the flag is set. If it
has odd number of 1s, flag is reset.
• C (Carry) flag − If arithmetic operation result is in a carry, the carry flag is set, otherwise it is reset.
(01+FF = 00000000 , CY=1)
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 14
16. GENERAL PURPOSE REGISTERS
• 8-bit B and C registers can be utilized as one 16-bit BC register pair. When used
as a pair the 8 bit C register contains low-order byte.
• MOV B,C
• 8-bit D and E registers can be used as one 16-bit DE register pair. When DE
register used as a pair the E register contains low-order byte.
• 8-bit H and L registers can be used as one 16-bit HL register pair. When HL
registers used as a pair the L register contains low-order byte. HL register
generally contains a DATA POINTER used to reference memory addresses.
(MOV A,M)
• LXI H,4500
• H 45 L 00
• MOV A,M
• A [M]
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 16
17. PROGRAM COUNTER
(PC)
• 16 bit register used as MEMORY POINTER.
• It stores the memory address of the next instruction to be
executed.
• This 16-bit register sequencing the execution of
instructions.
• When an opcode is being fetched, the program counter
value is incremented by one to point to the next memory
location.
• The program counter is set to 0000H.
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 17
18. STACK POINTER (SP):
• The stack pointer is also a 16-bit register used as a MEMORY
POINTER.
• It points to a memory location in Read /Write memory, called the
stack.
• The beginning of the stack is defined by loading a 16-bit address
in the stack pointer (register).
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 18
19. INSTRUCTION REGISTER AND INSTRUCTION
DECODER
• Instruction register is an 8 bit register. It is not accessible to the user
by program or instruction.
• When an instruction is fetched from memory to microprocessor, it is
loaded in the instruction register. The instruction decoder decodes the
instruction and establishes the sequence of events to follow.
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 19
20. 1) Fetch
2) Decode
3) Execute
A0-
A15
D0-D7
000001
10
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 20
21. TIMING AND CONTROL UNIT
• Timing and control unit synchronizes all the microprocessor operations with the clock and
generates the control signals required for communication between the microprocessor
and peripherals.
• THREE CONTROL SIGNALS: ALE, WR (Active low) and RD (Active low)
•THREE STATUS SIGNALS: IO/M (Active low), S0 and S1.
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 21
22. THE CONTROL SIGNALS
• ALE: Address Latch Enable. This signal is a pulse that become 1 when the AD0 – AD7 lines have
an address on them. It becomes 0 after that. This signal can be used to enable a latch to save the
address bits from the AD lines.
• RD: Read. Active low indicates that the data must be read from the selected memory location or I/O
port.
• WR: Write. Active low indicates that the data must be written into the selected memory location or
I/O port.
•
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 22
24. THE STATUS SIGNALS
• • IO/M: This signal specifies whether the operation is a memory operation (IO/M=0) or an I/O operation
(IO/M=1).
• S1 and S0 : Status signals to specify the kind of operation being performed.
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 24
25. CONTROL AND STATUS SIGNAL
IO/M
(active low)
RD (active
low)
WR (active
low)
S1 S0
Data Bus status
(Output)
0 0 0 0 0 Halt
0 1 0 0 1 Memory write
0 0 1 1 0 Memory read
1 1 0 0 1 IO write
1 0 1 1 0 IO read
0 0 1 1 1 Opcode fetch
1 1 1 1 1
Interrupt
acknowledgeCHAIRMA LAKSHMI K R AP/EIE/RMKEC 25
26. READY Pin 35 (Input)
This pin is used to synchronize
slower peripheral devices with fast
microprocessor.
A low value causes the
microprocessor to enter into wait
state.
The microprocessor remains in wait
state until the input at this pin goes
high.
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 26
27. SERIAL DATA TRANSFER
SID AND SOD
Pin 4 (Input) and Pin 5 (Output)
SID (Serial Input Data):
o It takes 1 bit input from serial
port of 8085.
o Stores the bit at the 8th position
(MSB) of the Accumulator.
o RIM (Read Interrupt Mask)
instruction is used to transfer
the bit.
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 27
28. SID AND SOD
Pin 4 (Input) and Pin 5 (Output)
SOD (Serial Output Data):
o It takes 1 bit from Accumulator to
serial port of 8085.
o Takes the bit from the 8th position
(MSB) of the Accumulator.
SIM (Set Interrupt Mask) instruction is used
to transfer the bit.
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 28
29. FOR OTHER MODULES, REFER BELOW LINK
• Module 1: Introduction of 8085
• Module 3: Interrupts
• Module 4: Data transfer Concepts
• Module 5: Timing Diagram
• Module 6: Memory Organization
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 29
