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Phase Change memory
- 1. Phase Change Memory(PCM) “No one will need more than 637KB of memory for a personal computer. 640KB ought to be enough for anybody,” :Bill Gates (1981) Jibin George Mathews, 06142, S7 EA, Department of Electronics and Communication
- 2. History Dr. Ovshinsky -1960s He formed his company ECD(Energy conversion devices) Article in 1970 September 28 edition of Electronics magazine by him & Gordon Moore titled “non volatile & reprogrammable ” 2000 – STMicroelectronics & ovonyx What is Phase Change Memory ? ”PCM/PRAMuses the unique behavior of chalcogenide glass, which can be "switched" between two states, crystalline and amorphous, with the application of heat.”
- 3. Technology to produce high purity thin films Cost Numerous breakthroughs in chalcogenide materials. Scaling - Less material to heat –less energy reqd. Flash memory will soon reach its scaling limit. Why PCM is becoming attractive now ??
- 7. CPU derives data from ROM &performs POST
- 8. Loads BIOS from ROM
- 9. Loads OS from HDD into RAM
- 10. Opening applications will load them into RAM.Saving them causes them to be written to the storage device and file deleted from RAMWhy does a computer need so many memory systems ?
- 12. Current NVM performance is stagnating! forever! density is improving! for how long? Answer is PCM !!
- 14. Faster writes
- 15. Faster execution
- 16. Non volatile
- 18. Low voltage (0.4-2 V)
- 19. Scaling: good
- 21. High voltage (10-15 V)
- 22. Scaling: bad
- 27. 4.PCM-Cell element characteristics Figure 2 – Entire cell diagram Basic Device Operation
- 29. PCM devices are programmed by electrically altering the structure (amorphous or crystalline)of a small volume of chalcogenide alloy
- 30. The programming pulse drives the memory cell into a high or low resistance state(phase transition process), depending on current magnitude.
- 32. High switching speed (~ns)
- 37. At low voltages, the device exhibits either a low resistance (~1k) or high resistance (>100k), depending on its programmed state : READ region
- 38. For a reset device : V >Vth to program
- 40. low amplitude pulses at voltages less than Vth do not set the device. Once Vth is surpassed, the device switches to the dynamic on state and programmed resistance is dramatically reduced as crystallization of the material is achieved.
- 43. Chalcogenide or phase change alloys is a ternary system of Gallium, Antimony and Tellurium. Chemically it is Ge2Sb2Te5.
- 46. 2006 :Intel created a mass producible 128 module
- 47. 2008: Intel discovered 2 additional states effectively doubling the Capacity
- 48. 2008 End: Intel begins shipping beta version called Alverstone
- 50. Emerging technologies & PCM
- 52. Broadens system applications
- 53. – Embedded, System-On-a-Chip (SOC), other products
- 54. Highly scalable
- 55. Risk factors have been identified
- 56. Time to productize
- 57. More companies looking forward to OUM
- 59. www.ieee.org
- 66. Objective analysis pcm white paper August 2009 PCM – a 180 nm non volatile memory cell element technology forstand alone and embedded applications – Stefan Lai and TylerLowrey Current status of Phase change memory – Stefan Lai
- 67. THANK YOU !!
- 68. Any Questions ?!
Notes de l'éditeur
- Why it didn’t become practical then ?because the existing memories were far more economical.PCM was costly then.but this gap will soon close since PCM will become less costly than Dram in a few years. PCM in 1970 article required 25 V at 200 mA to drive statechange during a write.Todays PCM require power similar to that of Nand and Nor chips of today.Why its attractive?there will come a time when flash memory can no longer be shrunk..all developers agree…btitsnt until a few years..
- Dynamic memory : should be periodically refreshed or read or written into..otherwise contents would vanish..Nvrameg:CMOS..CMOS is an on-board semiconductor chippowered by a CMOS battery inside computers that stores information such as the system time and system settings foryour computer.
- 1 GB SDRAM in a computer primarySecondary :HDD 40 GBTertiary :160 GB tape catridge
- Whether it comes from input or harddisk it all goes to RAM first..Memory is part of a team …SATA and PATA
- Simple :NOR flash and SRAM…. Complx : NAND flash & DRAM
- The chalcogenic compound is surrounded by two electrodes along with a wire to the compound. This wire serves to heat the compound thus changing its state and resistance. The wire is heated through Joule heating whereby due to high resistance of the heating element, when current passes through it, it heats up a high temperature very quickly. 0 to 1 == high to low res.== amorphous to crystal == small current 1 to 0 == low to high res. == crystal to amorphous == larger curentRead takes very small current A layout for a whole memory element can be seen in figure 2. When both the bit line and word line are high, a current goes through the device. There are two different currents used to write to the device. A small current used to change the device from a 0 to a 1. The small current raises the temperature above the crystallization and lets it slowly to keep it in that state.A larger current is used to change the state from a 1 to a 0. This is done by melting the crystalline state and quickly cooling it to leave it in the amorphous state.
- When melted it loses all crystalline structure, and rapid cooling below glass transition temperature causes the material to be locked into its amorphous phase. This phase is very stable near room temperature, but the rate of nucleation and growth of crystallites increases exponentially as the melting temperature is approached. To switch the memory element back to its conductive state, the material is heated to a temperature between the glass transition temperature and the melting temperature, causing nucleation and crystal growth to rapidly occur over a period of several nanoseconds.
- The figure above shows I‐V characteristics of the OUM device.At low voltages, the device exhibits either a low resistance (~1k) or highresistance (>100k), depending on its programmed state. This is the readregion of operation. To program the device, a pulse of sufficient voltageis applied to drive the device into a high conduction “dynamic onstate”. For a reset device, this requires a voltage greater than Vth.Vth is the device design parameter and for current memoryapplication is chosen to be in the range of 0.5 to 0.9 V. to avoid readdisturb, the device read region as shown in the figure, is well below Vthand also below the reset regime.The device is programmed while it is in the dynamic on state. The finalprogrammed state of the device is determined by the current amplitudeand the pulse duration in the dynamic on state. The reciprocal slope ofthe I‐V curve in the dynamic on state is the series device resistance.
- The above figure shows the device read resistance resultingfrom application of the programming current pulse amplitude. Startingin the set condition, moving from left to right, the device continues toremain in SET state as the amplitude is increased. Further increase inthe pulse amplitude begins to reset the device with still further increaseresetting the device to a standard amorphous resistance. Beginningagain with a device initially in the RESET state, low amplitude pulses atvoltages less than Vth do not set the device. Once Vth is surpassed, thedevice switches to the dynamic on state and programmed resistance isdramatically reduced as crystallization of the material is achieved.Further increase in programming current further crystallizes thematerial, which drops the resistance to a minimum value. As theprogramming pulse amplitude is increased further, resetting again isexhibited as in the case above. Devices can be safely reset above thesaturation point for margin. Importantly, the right side of the curveexhibits direct overwrite capability, where a particular resistance valuecan be obtained from a programming pulse, irrespective of the priorstate of the material. The slope of the right side of the curve is the devicedesign parameter and can be adjusted to enable a multi‐ state memorycell.
- First implemented in international space station (ISS) by European space agency.Will appear in Chandrayaan II
- First implemented in international space station (ISS) by European space agency.Will appear in Chandrayaan II