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FPGA are a special form of Programmable logic devices(PLDs) with higher densities as compared to custom ICs and capable of implementing functionality in a short period of time using computer aided design (CAD) software....by mathewsubin3388@gmail.com

Publié dans : Formation, Technologie, Business


  1. 1. FPGA (FIELD PROGRAMMABLE GATE ARRAY) Presented by : Subin Mathew RASET Cochin
  2. 2. HISTORY <ul><li>Programmable Read Only Memory (PROM) </li></ul><ul><li>fuse programming </li></ul><ul><li>n- address i/p can implement n i/p logic fun. </li></ul><ul><li>Problem: </li></ul><ul><li>Area efficiency. </li></ul><ul><li>Programmable Logic Array (PLA) </li></ul><ul><li>Programmable AND plane followed by programmable or wired OR plane. </li></ul><ul><li>Sum of product form </li></ul><ul><li>Problem : </li></ul><ul><li>Two level programming adds delay </li></ul>
  3. 3. NEXT - <ul><li>Programmable Array Logic (PAL) </li></ul><ul><li>Programmable AND plane and fixed OR plane. </li></ul><ul><li>Flexible comparably. </li></ul><ul><li>All these PLA and PAL are Simple Programmable Logic Devices (SPLD). </li></ul><ul><li>Problem: </li></ul><ul><li>Logic plane structure grows rapidly with number of inputs </li></ul>
  4. 4. NEXT - <ul><li>To mitigate the problem </li></ul><ul><li>Complex Programmable Logic Devices (CPLD) </li></ul><ul><li>programmably interconnect multiple SPLDs. </li></ul><ul><li>Problem : </li></ul><ul><li>Extending to higher density difficult </li></ul><ul><li>Less flexibility </li></ul>
  6. 6. FPGA <ul><li>A Field Programmable Gate Array (FPGA) is a Programmable Logic Device(PLD) with higher densities and capable of implementing different functions in a short period of time. </li></ul><ul><li>Topics covered:- </li></ul><ul><ul><ul><li>FPGA Overview </li></ul></ul></ul><ul><ul><ul><li>Logic Block </li></ul></ul></ul><ul><ul><ul><li>FPGA Routing Techniques </li></ul></ul></ul><ul><ul><ul><li>Programming Methodology </li></ul></ul></ul><ul><ul><ul><li>FPGA Design Flow </li></ul></ul></ul>
  7. 7. FPGA OVERVIEW <ul><li>2-D array of logic blocks and flip-flops with programmable interconnections. </li></ul><ul><li>Compact design </li></ul><ul><li>User can configure </li></ul><ul><ul><li>Intersections between the logic blocks </li></ul></ul><ul><ul><li>The function of each block </li></ul></ul>
  8. 8. WORLD OF INTEGRATED CIRCUITS Full-Custom ASICs Semi-Custom ASICs User Programmable PLD FPGA Why do we need FPGAs?
  9. 9. WHICH WAY TO GO? Low development cost Short time to market Reprogrammable High performance ASIC s FPGA s Low power Low cost in high volumes
  10. 10. OTHER FPGA ADVANTAGES <ul><li>Manufacturing cycle for ASIC is very costly, lengthy and engages lots of manpower </li></ul><ul><li>Mistakes not detected at design time have large impact on development time and cost </li></ul><ul><li>FPGAs are perfect for rapid prototyping of digital circuits </li></ul><ul><li>Easy upgrades like in case of software </li></ul><ul><li>Unique applications </li></ul>
  11. 11. LOGIC BLOCKS <ul><li>Purpose: to implement combinational and sequential logic functions. </li></ul><ul><li>Logic blocks can be implemented by:- </li></ul><ul><ul><li>Transistor pairs </li></ul></ul><ul><ul><li>Multiplexers </li></ul></ul><ul><ul><li>Look up tables( LUT) </li></ul></ul><ul><ul><li>Wide fan-in AND-OR structure. </li></ul></ul><ul><li>Granularity: is the hardware abstraction level. </li></ul><ul><li>According to granularity, two types of Blocks : </li></ul><ul><li>Fine Grain Logic Blocks </li></ul><ul><li>Coarse Grain Logic Blocks </li></ul>
  12. 12. FINE GRAIN <ul><li>The Cross Point FPGA </li></ul><ul><li>Transistors are interconnected. </li></ul><ul><li>Logic block is implemented using transistor pair tiles. </li></ul>
  13. 13. <ul><li>2. Plessey FPGA :- </li></ul><ul><ul><li>2-input NAND gate forms basic building block </li></ul></ul><ul><ul><li>Static RAM programming technology </li></ul></ul>
  14. 14. FINE GRAIN <ul><li>Advantage: </li></ul><ul><li>Blocks are fully utilized. </li></ul><ul><li>Disadvantage: </li></ul><ul><li>Require large numbers of wire segments and programmable switches. </li></ul><ul><li>Need more area. </li></ul>
  15. 15. COARSE GRAIN LOGIC BLOCKS <ul><li>Many types exists according to implementations </li></ul><ul><li>Multiplexer Based and Look-up-Table Based are most common </li></ul><ul><li>1. The Xilinx Logic Block: </li></ul><ul><ul><li>A SRAM function as a LUT. </li></ul></ul><ul><ul><li>Address line of SRAM as input </li></ul></ul><ul><ul><li>Output of SRAM gives the logic output </li></ul></ul><ul><ul><li>k-input logic function =2^k size SRAM </li></ul></ul><ul><ul><li>K-i/p LUT gives 2^2^k logic functions </li></ul></ul>
  16. 16. <ul><li>Advantage: </li></ul><ul><ul><li>High functionality </li></ul></ul><ul><ul><li>k inputs logic block can be implemented in no. of ways </li></ul></ul><ul><li>Disadvantage: </li></ul><ul><ul><li>Large no of memory cells required if i/p is large </li></ul></ul>
  17. 17. <ul><li>2 . Altera logic block:- </li></ul><ul><ul><li>Wide fan-in </li></ul></ul><ul><ul><li>Up to 100 i/p AND gate fed into OR gate with 3-8 i/ps </li></ul></ul><ul><li>Advantage:- </li></ul><ul><ul><li>Few logic block can implement the entire functionality </li></ul></ul><ul><ul><li>Less area required </li></ul></ul><ul><li>Disadvantage:- </li></ul><ul><ul><li>If i/ps are less, usage density of block will be low </li></ul></ul><ul><ul><li>Pull up devices consume static power </li></ul></ul>
  18. 18. EFFECTS OF GRANULARITY ON FPGA DENSITY AND PERFORMANCE <ul><li>Tradeoff </li></ul><ul><li>Granularity increase -> Blocks less </li></ul><ul><li>More Functional Blocks-> more area </li></ul><ul><li>Area is normally measured by total number of bits needed to implement the design. So look the example </li></ul>
  19. 19. EXAMPLE
  20. 20. FPGA ROUTING TECHNIQUES <ul><li>Comprises of programmable switches and wires </li></ul><ul><li>Provides connection between I/O blocks, logic blocks etc. </li></ul><ul><li>Routing decides logic block density and area consumed </li></ul><ul><li>Different routing techniques are:- </li></ul><ul><ul><li>Xilinx Routing architecture </li></ul></ul><ul><ul><li>Actel routing methodology </li></ul></ul><ul><ul><li>Altera routing methodology </li></ul></ul>
  21. 21. <ul><li>Xilinx Routing architecture </li></ul><ul><li>connections are made through a connection block. </li></ul><ul><li>SRAM is used to implement LUT. So connection sites are large </li></ul><ul><li>Pass transistors for connecting output pins </li></ul><ul><li>multiplexers for input pins. </li></ul><ul><li>wire segments used are:- </li></ul><ul><ul><li>general purpose segments </li></ul></ul><ul><ul><li>Direct interconnect </li></ul></ul><ul><ul><li>long line </li></ul></ul><ul><ul><li>clock lines </li></ul></ul>
  22. 22. <ul><li>Actel routing methodology </li></ul><ul><li>more wire segments in horizontal direction. </li></ul><ul><li>i/p & o/p vertical tracks can make connection with every horizontal track. </li></ul><ul><li>Routing is flexible. </li></ul><ul><li>Drawback:- </li></ul><ul><ul><ul><li>more switches are required => more capacitive load. </li></ul></ul></ul>
  23. 23. <ul><li>Altera routing methodology </li></ul><ul><li>It has two level hierarchy. </li></ul><ul><li>first level => 16 or 32 of the logic blocks are grouped into a Logic Array Block(LAB) </li></ul><ul><li>connections are formed using EPROM </li></ul><ul><li>Second level=> LABs are interconnected using Programmable Interconnect Array(PIA) </li></ul>
  24. 24. PROGRAMMING METHODOLOGY <ul><li>Electrically programmable switches are used to program FPGA </li></ul><ul><li>Properties of programmable switch determine on- resistance, parasitic capacitance, volatility, reprogrammability, size etc. </li></ul><ul><li>Various programming techniques are:- </li></ul><ul><ul><li>SRAM programming technology </li></ul></ul><ul><ul><li>Floating Gate Programming </li></ul></ul><ul><ul><li>Antifuse programming methodology </li></ul></ul>
  25. 25. <ul><li>SRAM programming technology </li></ul><ul><li>Use Static RAM cells to control pass gates or multiplexers. </li></ul><ul><li>1= closed switch connection </li></ul><ul><li>0= open </li></ul><ul><li>For mux, SRAM determines the mux input selection process. </li></ul><ul><li>Advantage </li></ul><ul><li>Fast re-programmability </li></ul><ul><li>Standard IC fabrication Tech. is used </li></ul><ul><li>Disadvantage </li></ul><ul><li>SRAM volatile </li></ul><ul><li>Requires large area </li></ul>
  26. 26. <ul><li>Floating gate programming </li></ul><ul><li>Tech used in EPROM and EEPROM devices is used </li></ul><ul><li>Switch is disable by applying high voltage to gate-2 between gate-1 and drain. </li></ul><ul><li>The charge is removed by UV light </li></ul><ul><li>Advantage:- No external permanent memory is needed to program it at power-up </li></ul><ul><li>Disadvantage:- </li></ul><ul><ul><li>Extra processing steps </li></ul></ul><ul><ul><li>Static power loss due to pull up resistor and high on resistance </li></ul></ul>
  27. 27. <ul><li>Antifuse programming methodology </li></ul><ul><li>2 terminal device with an un programmed state present very high resistance. </li></ul><ul><li>By applying high voltage create a low resistance link. </li></ul><ul><li>Advantage:- </li></ul><ul><li>Small size </li></ul><ul><li>Low series resistance and low parasitic capacitance </li></ul>
  28. 28. SUMMARY
  29. 29. WHY BETTER ? <ul><li>FPGA programmed using electrically programmable switches </li></ul><ul><li>Routing architectures are complex. </li></ul><ul><li>Logic is implemented using multiple levels of lower fan-in gates. </li></ul><ul><li>Shorter time to market </li></ul><ul><li>Ability to re-program in the field to fix bugs </li></ul>FPGA DISADVANTAGE <ul><li>FPGAs are generally slower than their application-specific integrated circuit (ASIC) </li></ul><ul><li>Can't handle as complex a design, and draw more power. </li></ul>
  30. 30. APPLICATION <ul><li>Reconfigurable computing. </li></ul><ul><li>Applications of FPGAs include DSP, software-defined radio. </li></ul><ul><li>The inherent parallelism of the logic resources on the FPGA allows for considerable compute throughput. </li></ul>
  31. 31. FPGA DESIGN AND PROGRAMMING <ul><li>To define the behavior of the FPGA the user provides a hardware description language (HDL) or a schematic design. </li></ul><ul><li>Then, using an electronic design automation tool, a technology-mapped net list is generated. </li></ul><ul><li>The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route. </li></ul><ul><li>The user will validate the map, place and route results via timing analysis, simulation, and other verification methodologies. </li></ul><ul><li>Once the design and validation process is complete, the binary file generated used to configure the FPGA. </li></ul>
  32. 32. THANK YOU