Double tail comparator

Analysis and Design of A Low-Voltage Low-Power Double-Tail
Comparator
Introduction
The comparator compares the voltages that appear at their inputs and outputs a voltage
representing the sign of the net difference between them. Comparators are important
elements in modern mixed signal systems. Speed and resolution are two important
features which are required for high speed applications such as on-chip high frequency
signal testing, data links, sense amplifiers and analog-to-digital converters. On-chip
testing of high frequency pseudo random binary sequences (PRBS) requires a high
speed comparator at the electrical interface stage 1,2
A clocked comparator generally consists of two stages. In that first stage is to interface
the input signals. The second (regenerative) stage consists of two cross coupled
inverters, where each input is connected to the output of the other. In a CMOS based
latch, the regenerative stage and its following stages consume low static power since
the power ground path is switched off either by a NMOS or PMOS transistor [10]. In
many applications comparator speed, power dissipation and transistor count are more
important. If comparator speed is a priority, the regenerative stage could be designed to
start its operation from midway between power supply and ground [6], for example,
conventional comparator2 [4]. However, the static power consumption is relatively high.
If comparator was designed with priority given to power reduction, then transistor count
increases thereby reducing the speed, for example double tail latched comparator or
conventional comparator1[4].
Comparator design largely depends on the target application. However, an input-
referred latch offset voltage (hence offset voltage), resulting from the device
mismatches such as threshold voltage Vth, current factor β (=μCoxW/L) and parasitic
node capacitance and output load capacitance mismatches, limits the accuracy of such

comparators [8], [9]. In this paper, we present a design of high-speed and low power
dissipating clocked comparator for stack circuit applications. The comparator is
attractive for the applications where both speed and power consumption are of the
highest priority.
The rest of the paper is organized as follows. The speed and power limitations of the
two conventional comparators design and areas for improvements are investigated in
Section II. An overview of the dynamic latched comparator design [13] is given in
Section III. Application of dynamic latched comparator in SAPTL was given in Section
CONVENTIONAL COMPARATORS
The circuit and schematic diagrams of the comparator presented in [3] are shown in Fig.
1. This comparator is compared with our design because of its speed and suitability for
low supply voltage applications. In the rest of the paper it will be referred to as
conventional comparator1.It operates in 2 phases 1)Reset phase 2)Regeneration phase
.While the clock is low(reset phase), M7 and M8 transistors are ON. M9 transistor is off.
As M7 and M8 transistors are ON Di+ and Di- nodes are pre-charged to Vdd. So M10
and M11 become ON and discharge the output nodes OUT+ and OUT- to ground. While
the clock is high (regeneration phase), M9 and M12 transistors are in ON condition. M7
and M8 transistors are in OFF state. So Di nodes starts discharging as M9 is ON. The
difference between voltages of Di+ and Di- (ΔVDi) are given to M10 and M11
transistors. As Di nodes starts discharging, M10 and M11 are initially in ON condition
and gradually M10 and M11 becomes OFF. Output nodes OUT+ and OUT- starts
regenerating when M10 and M11 are unable to ground the outputs. The intermediate
stage formed by M10 and Mll passes ΔVDi to the cross-coupled inverters and also
provides additional shielding between the input and output, ith less kickback noise as a
result.The conventional comparator2 is composed of two stages as shown in Fig. 3. The
first stage is the amplification stage, which consists of the transistors M1–M4 and M9.
The second stage is the regenerative stage that is comprised of the transistors M5– M8
and M10. The circuit works in two phases, namely the amplification phase and the
regenerative (evaluation) phase. When the clock (CLK) is low (amplification phase), the
tail transistor M9 turns ON and M10 turns OFF. When CLK was LOW only amplification

stage works here. In addition, the amplification stage is designed to produce its output
close to VDD-|Vthp| which can effectively reduce the charging time. In this stage Vp-Vn
is amplified and fed to regenerative stage. When the clock (CLK) is high (regeneration
phase), M10 turns ON and M9 turns OFF. Only regenerative stage works here. There is
a reduction of the delay time in the conventional comparator2 over the conventional
comparator1. Since the conventional comparator2 uses an amplification stage, it
consumes static power during the amplification period and hence the energy
consumption in the conventional comparator2 becomes higher than the conventional
comparator1.
There is a reduction of the power dissipation in the conventional comparator1 over the
conventional comparator2. In order to avoid these drawbacks in conventional
comparators, dynamic latched comparator was introduced in the subsequent section.
THE DYNAMIC LATCHED COMPARATOR
The dynamic latched comparator is composed of two stages as shown in Fig. 5. The
first stage is the interface stage which consists of all the transistors except two cross
coupled inverters. The second stage is the regenerative stage that is comprised of the
two cross coupled inverters, where each input is connected to the output of the other. It
operates in two phases.
1) Interface phase
2) Regeneration phase.
It consists of single nmos tail transistor connected to ground. When clock is low tail
transistor is off and depending on Vp and Vn output reaches to VDD or gnd. When clock
is high tail transistor is on and both the outputs discharges to ground. Since the
comparator offset [11] can be reduced by using known techniques [3], the main focus of
this paper is the comparator speed and power dissipation. Simulation comparing the
delay versus the supply voltage and power dissipation versus the supply voltage of the
comparator 1.2V supply has been done. The results show that the dynamic latched
comparator outperforms the other 2. Hence the 2 conventional and the dynamic latched
comparator will be compared. The layouts are automatically extracted and simulated

with a microwind simulator. Fig. shows simulation results of the power dissipation, delay
versus supply voltages (Vdd) respectively for the dynamic latched comparator and
conventional designs. The results show that the dynamic latched comparator circuit has
less delay time and less power dissipation than the conventional designs. As in the
dynamic latched comparator circuit design, both the power dissipation and delay will be
less [13] as shown in table1. This makes the dynamic latched comparator circuit more
attractive for the low power and high speed applications. Both conventional comparators
and dynamic latched comparator are used
1) To compare the outputs of stack circuit.
2) Clocked comparator combined with stack circuit acts as
OR (or) NOR circuit.
The basic architecture of clocked comparator based PTL is
shown in the Figure.
It consists of
1) The pass transistor tree, called the stack. It computes the
required logic function.
2) The root driver (inverter) injects signals into the stack and
3) The sense amplifier replaced with clocked comparator is
used to compare the stack outputs and also to perform NOR
(or) OR operation.

Stack:
The stack circuit consists of an NMOS pass transistors only. Full-swing inputs are
provided to the stack circuit and low swing pseudo differential outputs are obtained to
perform the required logic functions. Fig shows the logical paths of stack circuit that can
be connected according to Boolean function using the programmable switches.
As shown in fig by using the programmable switches, the stack implements a given
Boolean expression by connecting the minterm branches of the tree to one output ‘s’
and the maxterm branches to the other output ‘sn’ such that by drawing karnaugh map
we must obtain Boolean expression of OR gate . Consider the Boolean function of OR
(or) NOR gate. In this case for the stack circuit if we provide ‘Vin’ as ‘1’ then due to
inverter, ‘0’ will be provided to stack circuit and stack circuit performs NOR operation. If
we provide ‘Vin’ as ‘0’ then due to inverter, ‘1’ will be provided to stack circuit and stack
circuit performs OR operation.

Karnaugh map was drawn from fig corresponding toconnection of programmable
switches. According to karnaugh map the cells that consist of 1’s are termed
asminterms(01,10,11), and the cells that consist of 0’s aretermed as maxterms(00).
From the karnaugh map we get boolean equation of OR gate i.e A+B. In stack circuit all
the minterms(01,10,11) are connected to ‘s’ output and all the maxterms(00) are
connected to output ‘sn’ as shown in fig 10 to perform OR or NOR operation.
Driver:
Since the stack has no supply rail connections, a driver, which is a simple inverter, is
placed at the root input of the stack, to inject the evaluation current.
Clocked comparator:
In fig7 sense amplifier was used to recover both voltage swing and performance. If we
place either of the conventional comparators or dynamic latched comparator in place of
sense amplifier, it is useful to perform two operations. a) To compare the outputs of the
stack circuit. As the designed stack circuit performs NOR (or) OR operation, this NOR
(or) OR outputs are compared by the clocked comparator. b) Combination of both
Clocked comparator and stack can also be used as NOR (or) OR circuit. I.e. the output
of clocked comparator based PTL (stack) is same as stack circuit (NOR (or) OR circuit).

INTRODUCTION TO SOFTWARE USED
Modelsim 6.3 G
BACKGROUNT DETAILS:
Designers of digital systems are inevitably faced with the task of testing
their designs. Each design can be composed of many components, each of which
has to be tested in isolation and then integrated into a design when it operates
correctly. To verify that a design operates correctly we use simulation, which is a
process of testing the design by applying inputs to a circuit and observing its
behavior. The output of a simulation is a set of waveforms that show how a circuit
behaves based on a given sequence of inputs. The general flow of a simulation is
shown in below Figure. There are two main types of simulation: functional and
timing simulation. The functional simulation tests the logical operation of a circuit
without accounting for delays in the circuit. Signals are propagated through the
circuit using logic and wiring delays of zero. This simulation is fast and useful for
checking the fundamental correctness of the designed circuit. The second step of
the simulation process is the timing simulation. It is a more complex type of
simulation, where logic components and wires take some time to respond to input
stimuli. In addition to testing the logical operation of the circuit, it shows the
timing of signals in the circuit. This type of simulation is more realistic than the
functional simulation; however, it takes longer to perform.

VHDL
BACKGROUNT DETAILS:
VHDL is an acronym which stands for VHSIC Hardware Description
Language. VHSIC is yet another acronym which stands for Very High Speed
Integrated Circuits. If you can remember that, then you're off to a good start. The
language has been known to be somewhat complicated. The acronym does have a
purpose, though; it is supposed to capture the entire theme of the language that is
to describe hardware much the same way we use schematics.
VHDL can wear many hats. It is being used for documentation,
verification, and synthesis of large digital designs. This is actually one of the key
features of VHDL, since the same VHDL code can theoretically achieve all three
of these goals, thus saving a lot of effort. In addition to being used for each of these
purposes, VHDL can be used to take three different approaches to describing
hardware. These three different approaches are the structural, data flow, and
behavioral methods of hardware description. Most of the time a mixture of the
three methods is employed. The following sections introduce you to the language
by examining its use for each of these three methodologies. There are also certain
guidelines that form an approach to using VHDL for synthesis.

VHDL is a standard (VHDL-1076) developed by IEEE (Institute of
Electrical and Electronics Engineers). The language has been through a few
revisions, and you will come across this in the VHDL community. Currently, the
most widely used version is the 1987 (STD 1076-1987) version, sometimes
referred to as VHDL'87, but also just VHDL. However, there is a newer revision of
the language referred to as VHDL'93. VHDL'93 (adopted in 1994 of course) is
fairly new and is still in the process of replacing VHDL'87.
VHDL is an IEEE and U.S. Department of Defense standard for electronic
system descriptions. It is also becoming increasingly popular in private industry as
experience with the language grows and supporting tools become more widely
available. Therefore, to facilitate the transfer of system description information, an
understanding of VHDL will become increasingly important.

INTRODUCTION TO LOW POWER DESIGN
Power Management Techniques
Designers have developed various low power management techniques to reduce
leakage power consumption. These techniques make use of some form of sleep
operation. Placing power gating structures is a well-known technique for reducing power
leakage during standby mode, while maintaining high speeds in active mode. During
standby one or more portions of the circuit are switched off and the passage from the
source to ground is blocked, eliminating leakage in those areas. One side effect of
power gating is that data in the storage elements can be lost. As a result, designers use
retention memory elements to retain key state data during the sleep mode so that it can
be restored correctly upon power up. This is retention sleep mode. Some designs use a
conventional sleep operation in which the power supply of the entire design is cut off
when the circuit is not in use. Such designs do not require data to be retained in the
registers/latches used in the design. Power down in notebook computers is an example
of such a sleep mode. However, even with the conventional sleep operation, functional
verification of the design is required to ensure that the awake portions of the design
function properly while other parts are sleeping and that the system will operate
correctly when power is restored to the sleeping logic blocks.
With retention sleep mode, the operation of a logic circuit is stopped only if that specific
circuit is not in use. Some low power devices in portable equipment use retention sleep
mode during intermittent operations, such as waiting for input from a keyboard or
communicating through a slow interface. These devices resume operation without
restarting because the common registers and pipeline registers also preserve the data
during sleep. These sequential cells are known as retention flip-flops (RFF) or retention
latches (RLA). To implement sleep power management techniques, a well-defined
power management block (PMB) must be created with specific power control signals
and power domains (Figure 2).

Low Power Design and Verification Techniques 3
Power Management Design Structure
As the power management techniques employ turning off and on various segments of a
design, these designs are divided into different power domains, based on areas of
functionality that support common operations or tasks. In other words, a power domain
constitutes a collection of functionality that can be turned on or off as a whole, and it
runs at the same operating voltage level, having a single set of power control signals.
Power control signals are used to control sequential retention cells, isolation cells, and
the switches that serve as gatekeepers to a domain’s power supply.
In addition, every power aware design has at least one primary domain, which is always
on. This is known as either the wake-up or always-on domain.

Retention Memory Elements
To maintain the state of registers and latches during sleep mode, retention elements are
employed that can retain their data when in sleep mode. Alternatively, voltage threshold
scaling may be used for retention without requiring a bubble latch to hold the retained
value. RFFs and RLAs are affected by the power signals that control the RTL region to
which they belong. The registers are corrupted when the power is switched off [S.
Mutoh, et al. 1995]. Corruption is typically represented by X (unknown).
The register value is restored after power up if the value was saved successfully before
power down and the restore protocol executed successfully. Otherwise, the register
value remains unknown until it is set, reset, or a new value latched into it. These
elements will behave as normal memory elements when the power is switched on and
the power control signals are not asserted. An example of a retention flip-flop is a clock–
low retention FF. These types of RFFs have one control signal, known as RET. A clock-
low retention FF requires that the clock be gated low during the save Figure 2. Power
management design structure. [original Infineon diagram with added power domains]
and restore operations and most likely during power down retention as well. When RET
is asserted and the clock is low, clock–low retention FFs perform the save operation.
When RET is de-asserted and the clock is low, the restore operation is performed. They
behave as normal FFs when RET is low.
Isolation Cells
Isolation cells (also known as clamps) are logic gates that determine the values of a
power domain’s input or output port when the domain is powered down. (Note: A power
domain’s input and output ports are the ports on a logic block within the power domain
that is connected to a fan-out or fan-in located in another domain.) Isolation cells are
necessary because each power domain represents a design area comprised of
particular features, and each feature corresponds to an area of physical silicon. Even
though they may represent different power domains that can be independently powered

on and off, these areas of silicon remain physically connected; therefore, when one
domain is turned off, it is still connected electrically to other domains. For example,
when the MP3 component of a cell phone is turned off, it is still connected to the touch
pad circuitry, which remains on. This is a potential source of leakage, because
electricity seeks a balance in voltage level.
There are other reasons why it is important to control the values of a power domain’s
ports when it is powered down. For example, when a wire is used as a reset in a
downstream block that is powered on, it should not become active incidentally because
the power is shut down in an upstream domain (or temporarily toggles to an active level
during the wake-up power-on sequence). If it is active low, it may start as a 1, but if it
doesn’t continuously drive a 1, it could end up floating and drop below the threshold and
be seen as logic 0, causing that part of the design to reset when this is not intended. To
prevent this, the output of the upstream domain can be clamped to its current value, or
a specific value, when isolation is enabled just prior to power shut down. When the
clamp value is a “don’t care,” the typical default clamp value is 0 (low), as 0 is 0 at any
voltage level, eliminating the need for level shifting of the isolation value. Clamps
maintain the integrity of the downstream power domain. Thus, when one domain
powers off it does not corrupt elements that are still on. Similarly, it may be necessary to
isolate input ports. For example, a clock input signal to a domain’s logic should be gated
when the power is gated. Isolating the clock input signal is one way to implement clock
gating.
Moving Low Power Specification to the RTL
As mentioned earlier, power gating requires early verification. Waiting for the gate-level
netlist is too costly for a number of reasons, including slow simulation times and more
difficult debugging and problem resolution. In addition, information is needed at the RTL
to validate that low power techniques are implemented correctly in the early as well as
the final stages of the design flow.

Power information can be input at the RTL in two ways:
• Directly specified in the RTL code
• Indirectly specified via a side file.
By directly integrating the power information in RTL, it is guaranteed that the
corresponding power information is packaged together with the RTL. However, this
methodology has a number of disadvantages. It requires that any legacy RTL must be
updated to add power information. Organizations typically require full module or sub-
system re-verification when the RTL code is changed — a difficult and time-consuming
task. Most registers and latches in a RTL design are inferred and not explicitly coded as
part of the HDL; the RTL coding style would be significantly impacted if designers were
required to explicitly instantiate retention registers and latches wherever persistent state
information occurs. Furthermore, when designs go through a technology spin, there is
no guarantee that the retention cells will be functionally the same in the new technology
library. Similarly, explicit routing of power control signals to retention cells and the
instantiation of isolation cells and level shifters within the RTL code create an
unnecessarily tight coupling between the design functionality and the low power design
intent. Finally, as significant aspects of the low power design intent is related to the
technology implementation, it is usually modified more often than the RTL functional
specification.
Therefore, the two should be specified separately to facilitate maintenance, changes,
and verification. For these reasons, it makes sense to provide the power specification in
a side file. If the low power design intent is specified separately from the RTL code, yet
is related to it, then familiar RTL coding styles can be maintained and reuse of the RTL
maximized. Thus, a means of specifying the low power intent separately from the
functionality in RTL is not only very useful but also essential. The low power
specification side file should provide the information required to overlay the RTL
functionality with the power control network (PCN) and the power aware functionality.

The power specification data provides the low power design intent. The corruption
semantics (for that matter, any semantics) are implied by that intent. Thus, the power
specification captures the system’s power states; enough information about the power
supply network to know how the power supply is distributed and controlled for each
state; which registers need retention; how isolation and level shifting are handled; and
how retention is performed. This information can be used to functionally verify the
design at the RTL (or higher) and ensure that the low power design intent is
implemented in the gate-level design through synthesis. Synthesis tools can use the
same information to create an appropriate power aware gate-level netlist automatically.
UPF: A Portable Low Power Standard Format
Low power specifications are needed at each step of the design flow so that correct
power management components can be implemented at the RTL, inferred correctly
during synthesis, and placed-and-routed efficiently and accurately in the physical
design. This requires a single power format accepted by all tools in the flow at any given
abstraction level. A single power format eases implementation and validation and helps
meet design schedules. It must also address reusability, allow early and thorough
validation, and have built-in extensibility. Accellera, an organization focused on
identifying and creating new standards and methodologies for the electronic design
industry, recently approved a standard for low power design intent specification.

This standard is called the Unified Power Format (UPF).
Written in tcl, UPF captures the low power design specification in a portable form for
use in simulation, synthesis, and routing, reducing potential omissions during translation
of that intent from tool to tool. Because it is separate from the HDL description and can
be read by all of the tools in the flow, the UPF side file is as portable and interoperable
as the logic design’s HDL code.
Defining System Power States and the Supply Network
When designing the low power aspects of an electronic system, you should start by
defining the system power states. For example, a system power state may be such that
the modem is in sentinel mode, waiting for an incoming call; the information
management system is checking for scheduled appointments; and the rest of the
system is in sleep mode to conserve power. Such a deep sleep state must be defined in
terms of the functionality in the system. UPF provides two commands for defining a
power state table that captures the system power state information. The power state

table defines the power states in terms of the supply net states, ensuring integration of
the system power design with the low power design implementation. The UPF also
allows you to specify all the supply network information needed to verify and implement
the power supply distribution, and it provides the control required to realize the system
power states.
The supply network consists of power switches; supply ports that are defined for power
domains and power switches, supply nets that connect supply ports and logic ports and
propagate the supply state; and the supply states. Each supply port has one or more
supply states defined. The port may drive only Figure 3. The UPF side file provides a
consistent semantic for all tools throughout the design flow. one state at any given time.
That state is propagated by the supply net connected to the port. The power state table
is defined in terms of these states. UPF automates the connection of the supply network
to the logic elements in the design based on the semantics defined for specific types of
supply nets.
Specifying Power Domains
Power domains enable the automation of supply network connectivity for primary
supplies. A power domain is a collection of design logic elements that share a primary
supply. A primary supply consists of a single power and a single ground supply net pair.
This definition of a power domain enables the automatic connection of the primary
power and ground nets to all logic elements within the domain. For verification, UPF
specifies the semantics of power-off as primary power and/or primary ground are in the
off state. The behavioral semantics of power-down mirrors what happens in actual
hardware:
• All registers are corrupted.
• All signals driven by powered-down logic are corrupted.
• All behavioral processes within the powered-down domain are deactivated.

Equally important are the semantics for when power is restored to a domain. On power-
up:
• All combinatorial and latch (level sensitive) processes are evaluated, including
continuous assignment statements.
• Edge-triggered processes (flops) are not evaluated until the next active edge.
• All behavioral processes are re-enabled for evaluation.

MODULE DESCRIPTION
Module 1: Design of Dynamic Clocked Comparator
Comparator is the basic building block for the ADC
applications. This application module developed consist of a single-tail this comes under
the clocked regenerative comparator that can make fast decisions with the positive
feedback. The main parameters considered here are the clock inputs and with this the
double tail comparator is developed.
Module 2: Design of Double-Tail Comparator
This module is implemented to show the difference between
the dynamic clocked regenerative comparator and the double-tail comparator. The
conventional double tail comparator is developed and its delay analysis is performed.
The analysis results help to find out the disadvantages of the current double-tail
comparator design.
Module 3: Design of Auto Tunable Threshold Comparator
This module is designed with the tuanble threshold.Using the
auto-tunable threshold a comparator is capable of generating digital signal from analog
input which can achieve good tolerance and efficiency.This module helps to avoid the
kick-back noise and Mis-match in the existing double tail comparator design using auto-
tunable threshold.
Module 4: Design and Analysis of the Integration Module
We integrate all the sub-modules and their analysis and
performance are implemented with the Model Sim software simulation results.

DETAILED ABSTRACT
Design and analysis of Low-power, area efficient and high speed analog-to-digital
converters is pushing toward the use of dynamic comparators, which is used to
maximize speed and power efficiency. In the existing design, an analysis on the delay of
the dynamic comparators will be presented and analytical expressions are derived.
From the analytical expressions, designers can obtain an intuition about the main
contributors to the comparator delay and fully explore the tradeoffs in dynamic
comparator design. Based on the presented analysis, a new dynamic comparator is
proposed, where the circuit of a conventional double tail comparator is modified for low-
power and fast operation even in small supply voltages. Without complicating the design
and by adding few transistors, the positive feedback during the regeneration is
strengthened, which results in remarkably reduced delay time.
Post-layout simulation results in a 0.18-μm CMOS technology confirm the analysis
results. It is shown that in the proposed dynamic comparator both the power
consumption and delay time are significantly reduced. The maximum clock frequency of
the proposed comparator can be increased to 2.5 and 1.1 GHz at supply voltages of 1.2
and 0.6 V, while consuming 1.4 mW and 153 μW, respectively. The standard deviation
of the input-referred offset is 7.8 mV at 1.2 V supply.
Clocked regenerative comparators have found wide applications in many high-speed
ADC’s since they can make fast decisions due to the strong positive feedback in the
regenerative latch.Many comprehensive analyses have been presented,which
investigate the performance of these comparators from differents aspects, such as
noise offset,random decision errors and kick-back noise. In this design the dynamic
comparator is constructed, where the circuit of a conventional double tail comparator is
modified for low-power and fast operation even in small supply voltages. Without
complicating the design and by adding few transistors, the positive feedback during the
regeneration is strengthened, which results in remarkably reduced delay time.

Post-layout simulation results in a 0.18-μm CMOS technology confirm the analysis
results. It is shown that in the implemented dynamic comparator both the power
consumption and delay time are significantly reduced. As this design produce a Mis-
match and kick-back noise, a digitally controlled dual tail comparator is designed with
tunable threshold. Using the auto tunable threshold a comparator is capable of
generating the digital signal from analog input through a systematic manner which
achieves tolerance and efficiency.
PROPOSED BLOCK DIAGRAM

HARDWARE DESCRIPTIONS
FEATURES OF FPGA
• 5 ns pin-to-pin logic delays
• System frequency up to 178 MHz
• 72 macrocells with 1,600 usable gates
• Available in small footprint packages
- 44-pin PLCC (34 user I/O pins)
- 44-pin VQFP (34 user I/O pins)
- 48-pin CSP (38 user I/O pins)
- 64-pin VQFP (52 user I/O pins)
- 100-pin TQFP (72 user I/O pins)
- Pb-free available for all packages
• Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin

inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
ARCHITECTURE OF FPGA

SIMULATION RESULTS
RTL SCHEMATIC OUTPUT

DYNAMIC COMPARATOR
DYNAMIC COMPARATOR

DATA FLOW DIAGRAMS
DYNAMIC COMPARATOR

Double tail comparator

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