SlideShare une entreprise Scribd logo
1  sur  12
Direct Memory
Access
Introduction
 An important aspect governing the Computer
System performance is the transfer of data
between memory and I/O devices.
 The operation involves loading programs or data
files from disk into memory, saving file on disk,
and accessing virtual memory pages on any
secondary storage medium.
What is Direct Memory
Access (DMA) ?
 When large volumes of data are to be moved, a more
efficient technique is required: Direct Memory Access
(DMA)
 Blocks of data are transferred between an external
device and the main memory, without continuous
intervention by the processor.
Implementing DMA in a
Computer System
 A DMA controller implements direct memory access in
a computer system.
 It connects directly to the I/O device at one end and
to the system buses at the other end. It also interacts
with the CPU, both via the system buses and two new
direct connections.
 It is sometimes referred to as a channel. In an
alternate configuration, the DMA controller may be
incorporated directly into the I/O device.
DMA Controller
 DMA controller is part of the I/O interface.
 Performs the functions that would normally be
carried out by the processor when access main
memory. For each word transferred, it provides
the memory address and all the bus signals that
control data transfer.
DMA Controller
 Although DMAC can transfer data without intervention by the
processor, it’s operation must be under the control of a
program executed by the processor.
 To initiate the transfer of a block of data, the processor sends
the starting address, the number of words in the block, and
direction of the transfer. Once information is received, the
DMAC proceeds to perform the requested operation. When
the entire block has been transferred, the controller informs
the processor by raising an interrupt signal.
How is OS involved
 I/O operations are always performed by the OS in response to a
request from an application program.
 OS is also responsible for suspending the execution of one
program and starting another.
 OS puts the program that requested the transfer in the
Blocked state,
 initiates the DMA operation,
 starts execution of another program.
 When the transfer is complete, the DMA controller informs the
processor by sending an interrupt request.
 OS puts suspended program in the Runnable state so that it
can be selected by the scheduler to continue execution.
Fig - DMA Block Diagram
Whether a read or write is requested, using the read or write control
line between the processor and the DMA module
The address of the I/O device involved, communicated on the data lines
The starting location in memory to read from or write to, communicated
on the data lines and stored by the DMA module in its address register
The number of words to be read or written, again communicated via the
data lines and stored in the data count register
Steps in a DMA operation
• Processor initiates the DMA controller
• Gives device number, memory buffer pointer, …
• Called channel initialization
• Once initialized, it is ready for data transfer
processor DMA controller
Gives
device
number
I/O device number
Fig - DMA Configuration
a) All modules share the same system bus. The DMA module, acting as a surrogate processor, uses
programmed I/O to exchange data between memory and an I/O module through the DMA.
b) This means that there is a path between the DMA module and one or more I/O modules that does
not include the system bus.
c) All modules share the same system bus. The DMA module, acting as a surrogate processor, uses
programmed I/O to exchange data between memory and an I/O module through the DMA
Summary
 Advantages of DMA
 Computer system performance is improved by direct
transfer of data between memory and I/O devices,
bypassing the CPU.
 CPU is free to perform operations that do not use
system buses.
 Disadvantages of DMA
 In case of Burst Mode data transfer, the CPU is
rendered inactive for relatively long periods of time.

Contenu connexe

Tendances

8237 dma controller
8237 dma controller8237 dma controller
8237 dma controller
Tech_MX
 
Cache memory
Cache memoryCache memory
Cache memory
Anuj Modi
 

Tendances (20)

DMA presentation [By- Digvijay]
DMA presentation [By- Digvijay]DMA presentation [By- Digvijay]
DMA presentation [By- Digvijay]
 
Cache memory ppt
Cache memory ppt  Cache memory ppt
Cache memory ppt
 
Microprogrammed Control Unit
Microprogrammed Control UnitMicroprogrammed Control Unit
Microprogrammed Control Unit
 
8257 DMA Controller
8257 DMA Controller8257 DMA Controller
8257 DMA Controller
 
Direct memory access (dma)
Direct memory access (dma)Direct memory access (dma)
Direct memory access (dma)
 
Dram and its types
Dram and its typesDram and its types
Dram and its types
 
Computer architecture input output organization
Computer architecture input output organizationComputer architecture input output organization
Computer architecture input output organization
 
Modes of transfer
Modes of transferModes of transfer
Modes of transfer
 
8237 dma controller
8237 dma controller8237 dma controller
8237 dma controller
 
Computer organization memory
Computer organization memoryComputer organization memory
Computer organization memory
 
Memory organization (Computer architecture)
Memory organization (Computer architecture)Memory organization (Computer architecture)
Memory organization (Computer architecture)
 
Memory hierarchy
Memory hierarchyMemory hierarchy
Memory hierarchy
 
Cache memory
Cache  memoryCache  memory
Cache memory
 
80286 microprocessor
80286 microprocessor80286 microprocessor
80286 microprocessor
 
Direct Memory Access & Interrrupts
Direct Memory Access & InterrruptsDirect Memory Access & Interrrupts
Direct Memory Access & Interrrupts
 
Data transfer and manipulation
Data transfer and manipulationData transfer and manipulation
Data transfer and manipulation
 
Module4
Module4Module4
Module4
 
Control unit design
Control unit designControl unit design
Control unit design
 
Cache memory
Cache memoryCache memory
Cache memory
 
memory hierarchy
memory hierarchymemory hierarchy
memory hierarchy
 

Similaire à Dma

discuss the drawbacks of programmed and interrupt driven io and des.pdf
discuss the drawbacks of programmed and interrupt driven io and des.pdfdiscuss the drawbacks of programmed and interrupt driven io and des.pdf
discuss the drawbacks of programmed and interrupt driven io and des.pdf
info998421
 
Dma and dma controller 8237
Dma and dma controller 8237Dma and dma controller 8237
Dma and dma controller 8237
Ashwini Awatare
 

Similaire à Dma (20)

DMA airctecture.pptx
DMA airctecture.pptxDMA airctecture.pptx
DMA airctecture.pptx
 
DMA Versus Polling or Interrupt Driven I/O
DMA Versus Polling or Interrupt Driven I/ODMA Versus Polling or Interrupt Driven I/O
DMA Versus Polling or Interrupt Driven I/O
 
fathima.pptxjhvjhvjhvjhvhvjhchvhvjvjhvjhj
fathima.pptxjhvjhvjhvjhvhvjhchvhvjvjhvjhjfathima.pptxjhvjhvjhvjhvhvjhchvhvjvjhvjhj
fathima.pptxjhvjhvjhvjhvhvjhchvhvjvjhvjhj
 
coadma-150401131446-conversion-gate01.pptx
coadma-150401131446-conversion-gate01.pptxcoadma-150401131446-conversion-gate01.pptx
coadma-150401131446-conversion-gate01.pptx
 
discuss the drawbacks of programmed and interrupt driven io and des.pdf
discuss the drawbacks of programmed and interrupt driven io and des.pdfdiscuss the drawbacks of programmed and interrupt driven io and des.pdf
discuss the drawbacks of programmed and interrupt driven io and des.pdf
 
Input output in computer Orgranization and architecture
Input output in computer Orgranization and architectureInput output in computer Orgranization and architecture
Input output in computer Orgranization and architecture
 
ppppptttt.pdf
ppppptttt.pdfppppptttt.pdf
ppppptttt.pdf
 
DMA
DMADMA
DMA
 
Modes Of Transfer in Input/Output Organization
Modes Of Transfer in Input/Output OrganizationModes Of Transfer in Input/Output Organization
Modes Of Transfer in Input/Output Organization
 
Direct access memory
Direct access memoryDirect access memory
Direct access memory
 
Modes of data transfer
Modes of data transferModes of data transfer
Modes of data transfer
 
Dma and dma controller 8237
Dma and dma controller 8237Dma and dma controller 8237
Dma and dma controller 8237
 
I/O Management
I/O ManagementI/O Management
I/O Management
 
H n q & a
H n q & aH n q & a
H n q & a
 
Unit 4-input-output organization
Unit 4-input-output organizationUnit 4-input-output organization
Unit 4-input-output organization
 
Unit 4-input-output organization
Unit 4-input-output organizationUnit 4-input-output organization
Unit 4-input-output organization
 
Direct Memory Access (DMA).pptx
Direct Memory Access (DMA).pptxDirect Memory Access (DMA).pptx
Direct Memory Access (DMA).pptx
 
Direct memory access
Direct memory accessDirect memory access
Direct memory access
 
DMA_document__1696148675.pdf
DMA_document__1696148675.pdfDMA_document__1696148675.pdf
DMA_document__1696148675.pdf
 
Unit3 input
Unit3 inputUnit3 input
Unit3 input
 

Plus de Piyush Rochwani (20)

Unit 2
Unit 2Unit 2
Unit 2
 
Unit 3
Unit 3Unit 3
Unit 3
 
Biometrics based key generation
Biometrics based key generationBiometrics based key generation
Biometrics based key generation
 
Serial transmission
Serial transmissionSerial transmission
Serial transmission
 
Sequential and combinational alu
Sequential and combinational alu Sequential and combinational alu
Sequential and combinational alu
 
Memory virtualization
Memory virtualizationMemory virtualization
Memory virtualization
 
Risc
RiscRisc
Risc
 
Raid
Raid Raid
Raid
 
Pipelining and co processor.
Pipelining and co processor.Pipelining and co processor.
Pipelining and co processor.
 
Paging and segmentation
Paging and segmentationPaging and segmentation
Paging and segmentation
 
Page replacement algorithms
Page replacement algorithmsPage replacement algorithms
Page replacement algorithms
 
8086 Microprocessor
8086 Microprocessor8086 Microprocessor
8086 Microprocessor
 
Control unit
Control unitControl unit
Control unit
 
Memory types
Memory typesMemory types
Memory types
 
Solid state solid state drives
Solid state solid state drivesSolid state solid state drives
Solid state solid state drives
 
Coa INTERUPT
Coa INTERUPTCoa INTERUPT
Coa INTERUPT
 
Cisc(a022& a023)
Cisc(a022& a023)Cisc(a022& a023)
Cisc(a022& a023)
 
Booth’s algorithm.(a014& a015)
Booth’s algorithm.(a014& a015)Booth’s algorithm.(a014& a015)
Booth’s algorithm.(a014& a015)
 
06 floating point
06 floating point06 floating point
06 floating point
 
05 multiply divide
05 multiply divide05 multiply divide
05 multiply divide
 

Dernier

Russian Escort Service in Delhi 11k Hotel Foreigner Russian Call Girls in Delhi
Russian Escort Service in Delhi 11k Hotel Foreigner Russian Call Girls in DelhiRussian Escort Service in Delhi 11k Hotel Foreigner Russian Call Girls in Delhi
Russian Escort Service in Delhi 11k Hotel Foreigner Russian Call Girls in Delhi
kauryashika82
 
An Overview of Mutual Funds Bcom Project.pdf
An Overview of Mutual Funds Bcom Project.pdfAn Overview of Mutual Funds Bcom Project.pdf
An Overview of Mutual Funds Bcom Project.pdf
SanaAli374401
 
1029-Danh muc Sach Giao Khoa khoi 6.pdf
1029-Danh muc Sach Giao Khoa khoi  6.pdf1029-Danh muc Sach Giao Khoa khoi  6.pdf
1029-Danh muc Sach Giao Khoa khoi 6.pdf
QucHHunhnh
 
Seal of Good Local Governance (SGLG) 2024Final.pptx
Seal of Good Local Governance (SGLG) 2024Final.pptxSeal of Good Local Governance (SGLG) 2024Final.pptx
Seal of Good Local Governance (SGLG) 2024Final.pptx
negromaestrong
 
Gardella_PRCampaignConclusion Pitch Letter
Gardella_PRCampaignConclusion Pitch LetterGardella_PRCampaignConclusion Pitch Letter
Gardella_PRCampaignConclusion Pitch Letter
MateoGardella
 

Dernier (20)

Unit-IV- Pharma. Marketing Channels.pptx
Unit-IV- Pharma. Marketing Channels.pptxUnit-IV- Pharma. Marketing Channels.pptx
Unit-IV- Pharma. Marketing Channels.pptx
 
psychiatric nursing HISTORY COLLECTION .docx
psychiatric  nursing HISTORY  COLLECTION  .docxpsychiatric  nursing HISTORY  COLLECTION  .docx
psychiatric nursing HISTORY COLLECTION .docx
 
Russian Escort Service in Delhi 11k Hotel Foreigner Russian Call Girls in Delhi
Russian Escort Service in Delhi 11k Hotel Foreigner Russian Call Girls in DelhiRussian Escort Service in Delhi 11k Hotel Foreigner Russian Call Girls in Delhi
Russian Escort Service in Delhi 11k Hotel Foreigner Russian Call Girls in Delhi
 
INDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptx
INDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptxINDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptx
INDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptx
 
Grant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy ConsultingGrant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy Consulting
 
Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"
Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"
Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"
 
Paris 2024 Olympic Geographies - an activity
Paris 2024 Olympic Geographies - an activityParis 2024 Olympic Geographies - an activity
Paris 2024 Olympic Geographies - an activity
 
Application orientated numerical on hev.ppt
Application orientated numerical on hev.pptApplication orientated numerical on hev.ppt
Application orientated numerical on hev.ppt
 
An Overview of Mutual Funds Bcom Project.pdf
An Overview of Mutual Funds Bcom Project.pdfAn Overview of Mutual Funds Bcom Project.pdf
An Overview of Mutual Funds Bcom Project.pdf
 
Accessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impactAccessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impact
 
1029-Danh muc Sach Giao Khoa khoi 6.pdf
1029-Danh muc Sach Giao Khoa khoi  6.pdf1029-Danh muc Sach Giao Khoa khoi  6.pdf
1029-Danh muc Sach Giao Khoa khoi 6.pdf
 
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptxSOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
 
Mehran University Newsletter Vol-X, Issue-I, 2024
Mehran University Newsletter Vol-X, Issue-I, 2024Mehran University Newsletter Vol-X, Issue-I, 2024
Mehran University Newsletter Vol-X, Issue-I, 2024
 
ICT Role in 21st Century Education & its Challenges.pptx
ICT Role in 21st Century Education & its Challenges.pptxICT Role in 21st Century Education & its Challenges.pptx
ICT Role in 21st Century Education & its Challenges.pptx
 
How to Give a Domain for a Field in Odoo 17
How to Give a Domain for a Field in Odoo 17How to Give a Domain for a Field in Odoo 17
How to Give a Domain for a Field in Odoo 17
 
Class 11th Physics NEET formula sheet pdf
Class 11th Physics NEET formula sheet pdfClass 11th Physics NEET formula sheet pdf
Class 11th Physics NEET formula sheet pdf
 
Unit-V; Pricing (Pharma Marketing Management).pptx
Unit-V; Pricing (Pharma Marketing Management).pptxUnit-V; Pricing (Pharma Marketing Management).pptx
Unit-V; Pricing (Pharma Marketing Management).pptx
 
Seal of Good Local Governance (SGLG) 2024Final.pptx
Seal of Good Local Governance (SGLG) 2024Final.pptxSeal of Good Local Governance (SGLG) 2024Final.pptx
Seal of Good Local Governance (SGLG) 2024Final.pptx
 
Introduction to Nonprofit Accounting: The Basics
Introduction to Nonprofit Accounting: The BasicsIntroduction to Nonprofit Accounting: The Basics
Introduction to Nonprofit Accounting: The Basics
 
Gardella_PRCampaignConclusion Pitch Letter
Gardella_PRCampaignConclusion Pitch LetterGardella_PRCampaignConclusion Pitch Letter
Gardella_PRCampaignConclusion Pitch Letter
 

Dma

  • 2. Introduction  An important aspect governing the Computer System performance is the transfer of data between memory and I/O devices.  The operation involves loading programs or data files from disk into memory, saving file on disk, and accessing virtual memory pages on any secondary storage medium.
  • 3. What is Direct Memory Access (DMA) ?  When large volumes of data are to be moved, a more efficient technique is required: Direct Memory Access (DMA)  Blocks of data are transferred between an external device and the main memory, without continuous intervention by the processor.
  • 4. Implementing DMA in a Computer System  A DMA controller implements direct memory access in a computer system.  It connects directly to the I/O device at one end and to the system buses at the other end. It also interacts with the CPU, both via the system buses and two new direct connections.  It is sometimes referred to as a channel. In an alternate configuration, the DMA controller may be incorporated directly into the I/O device.
  • 5. DMA Controller  DMA controller is part of the I/O interface.  Performs the functions that would normally be carried out by the processor when access main memory. For each word transferred, it provides the memory address and all the bus signals that control data transfer.
  • 6. DMA Controller  Although DMAC can transfer data without intervention by the processor, it’s operation must be under the control of a program executed by the processor.  To initiate the transfer of a block of data, the processor sends the starting address, the number of words in the block, and direction of the transfer. Once information is received, the DMAC proceeds to perform the requested operation. When the entire block has been transferred, the controller informs the processor by raising an interrupt signal.
  • 7.
  • 8. How is OS involved  I/O operations are always performed by the OS in response to a request from an application program.  OS is also responsible for suspending the execution of one program and starting another.  OS puts the program that requested the transfer in the Blocked state,  initiates the DMA operation,  starts execution of another program.  When the transfer is complete, the DMA controller informs the processor by sending an interrupt request.  OS puts suspended program in the Runnable state so that it can be selected by the scheduler to continue execution.
  • 9. Fig - DMA Block Diagram Whether a read or write is requested, using the read or write control line between the processor and the DMA module The address of the I/O device involved, communicated on the data lines The starting location in memory to read from or write to, communicated on the data lines and stored by the DMA module in its address register The number of words to be read or written, again communicated via the data lines and stored in the data count register
  • 10. Steps in a DMA operation • Processor initiates the DMA controller • Gives device number, memory buffer pointer, … • Called channel initialization • Once initialized, it is ready for data transfer processor DMA controller Gives device number I/O device number
  • 11. Fig - DMA Configuration a) All modules share the same system bus. The DMA module, acting as a surrogate processor, uses programmed I/O to exchange data between memory and an I/O module through the DMA. b) This means that there is a path between the DMA module and one or more I/O modules that does not include the system bus. c) All modules share the same system bus. The DMA module, acting as a surrogate processor, uses programmed I/O to exchange data between memory and an I/O module through the DMA
  • 12. Summary  Advantages of DMA  Computer system performance is improved by direct transfer of data between memory and I/O devices, bypassing the CPU.  CPU is free to perform operations that do not use system buses.  Disadvantages of DMA  In case of Burst Mode data transfer, the CPU is rendered inactive for relatively long periods of time.