SlideShare une entreprise Scribd logo
1  sur  8
BINARY DECODERS
• A binary decoder is a multi-input, multi-output combinational
circuit that converts a binary code of n input lines into a one out
of 2n output code.These are used when there is need to
activate exactly one of 2n output based on an n-bit input value.
• The figure below shows the general structure of binary decoder
in which encoded information is accepted at n input lines and
the output is produced at 2n possible output lines.
2 to 4 BINARY DECODER
• The figure below shows the truth table for a 2-to-4 decoder.
For a given input, the outputsY0 throughY3 are active high if
enable input EN is active high (EN = 1).When both inputs A
and B are low (or A= B= 0), the outputY0 will be active or High
and all other outputs will be low.
• From the above truth table we can obtain Boolean expression
for the each output as
• These expressions can be implemented by using basic logic
gates.Thus, the logic circuit design of the 2-to-4 line decoder is
given below which is implemented by using NOT and AND
gates.Two NOT gates or inverters provide the complement of
inputs.
• A common enable line is connected to eachAND gate such that
when EN= 0 all the outputs are zero and if EN=1, depends on the
inputs A and B, outputs are produced. Each output represents
one of the minterms of the 2 input variables.
• It is also possible to design 2-to-4 decoder using NAND gates as
shown in figure below along with truth table.This is constructed
with a principle of max terms as outputs.To generate the
minterms, we have to use NAND gates which act as inverters. If
both inputs are zero (A = B = 0),Y0 will be zero , if A = 0 and B= 1,
thenY1 will be 1 and so on.
• Therefore, only one output will be low for any combinations of
inputs at a given time and all other outputs will be high.This type
of decoders is available in IC forms so that 3 to 8, 4 to 16, and 5 to
32 decoders can also be made depends on the application
requirement.

Contenu connexe

Tendances

Decoders
DecodersDecoders
Decoders
Re Man
 

Tendances (20)

Decoders
DecodersDecoders
Decoders
 
Sequential Logic Circuit
Sequential Logic CircuitSequential Logic Circuit
Sequential Logic Circuit
 
Encoder.pptx
Encoder.pptxEncoder.pptx
Encoder.pptx
 
Decoders-Digital Electronics
Decoders-Digital ElectronicsDecoders-Digital Electronics
Decoders-Digital Electronics
 
Encoders and decoders
Encoders and decodersEncoders and decoders
Encoders and decoders
 
Registers
RegistersRegisters
Registers
 
Sequential logic circuits flip-flop pt 1
Sequential logic circuits   flip-flop pt 1Sequential logic circuits   flip-flop pt 1
Sequential logic circuits flip-flop pt 1
 
Programmable Logic Devices Plds
Programmable Logic Devices PldsProgrammable Logic Devices Plds
Programmable Logic Devices Plds
 
VHDL-PRESENTATION.ppt
VHDL-PRESENTATION.pptVHDL-PRESENTATION.ppt
VHDL-PRESENTATION.ppt
 
Flip-Flop || Digital Electronics
Flip-Flop || Digital ElectronicsFlip-Flop || Digital Electronics
Flip-Flop || Digital Electronics
 
latches
 latches latches
latches
 
Introduction to Counters
Introduction to CountersIntroduction to Counters
Introduction to Counters
 
Parity Generator and Parity Checker
Parity Generator and Parity CheckerParity Generator and Parity Checker
Parity Generator and Parity Checker
 
SEQUENTIAL CIRCUITS [Flip-flops and Latches]
SEQUENTIAL CIRCUITS [Flip-flops and Latches]SEQUENTIAL CIRCUITS [Flip-flops and Latches]
SEQUENTIAL CIRCUITS [Flip-flops and Latches]
 
Encoder
EncoderEncoder
Encoder
 
(D/A) and (A/D)conversion
(D/A) and (A/D)conversion(D/A) and (A/D)conversion
(D/A) and (A/D)conversion
 
Counters
CountersCounters
Counters
 
J - K & MASTERSLAVE FLIPFLOPS
J - K & MASTERSLAVE FLIPFLOPSJ - K & MASTERSLAVE FLIPFLOPS
J - K & MASTERSLAVE FLIPFLOPS
 
Demultiplexer presentation
Demultiplexer presentationDemultiplexer presentation
Demultiplexer presentation
 
Logic families
Logic familiesLogic families
Logic families
 

En vedette

OS - CPU Scheduling
OS - CPU SchedulingOS - CPU Scheduling
OS - CPU Scheduling
vinay arora
 
G:\Advertidment & Public Relationing\Add 1
G:\Advertidment & Public Relationing\Add 1G:\Advertidment & Public Relationing\Add 1
G:\Advertidment & Public Relationing\Add 1
Anas
 
Discourse functions of relative clauses
Discourse functions of relative clausesDiscourse functions of relative clauses
Discourse functions of relative clauses
Jinhoon Yoo
 

En vedette (18)

Cda analysis of sunsilk pink commercial
Cda analysis of sunsilk pink commercialCda analysis of sunsilk pink commercial
Cda analysis of sunsilk pink commercial
 
Multiplexer and demultiplexer applications.ppsx 3
Multiplexer and demultiplexer applications.ppsx 3Multiplexer and demultiplexer applications.ppsx 3
Multiplexer and demultiplexer applications.ppsx 3
 
Decoder
DecoderDecoder
Decoder
 
RVC: A Multi-Decoder CAL Composer Tool
RVC: A Multi-Decoder CAL Composer ToolRVC: A Multi-Decoder CAL Composer Tool
RVC: A Multi-Decoder CAL Composer Tool
 
Ceng232 Decoder Multiplexer Adder
Ceng232 Decoder Multiplexer AdderCeng232 Decoder Multiplexer Adder
Ceng232 Decoder Multiplexer Adder
 
The decoder
The decoderThe decoder
The decoder
 
OS - CPU Scheduling
OS - CPU SchedulingOS - CPU Scheduling
OS - CPU Scheduling
 
G:\Advertidment & Public Relationing\Add 1
G:\Advertidment & Public Relationing\Add 1G:\Advertidment & Public Relationing\Add 1
G:\Advertidment & Public Relationing\Add 1
 
Discourse functions of relative clauses
Discourse functions of relative clausesDiscourse functions of relative clauses
Discourse functions of relative clauses
 
CDA and politics
CDA and politicsCDA and politics
CDA and politics
 
08 decoder
08 decoder08 decoder
08 decoder
 
Half subtracter
Half subtracterHalf subtracter
Half subtracter
 
計測対象をhttpからhttpsに変更する
計測対象をhttpからhttpsに変更する計測対象をhttpからhttpsに変更する
計測対象をhttpからhttpsに変更する
 
Binary Arithmetic Presentation about Binary Numbers 2015
Binary Arithmetic Presentation about Binary Numbers 2015Binary Arithmetic Presentation about Binary Numbers 2015
Binary Arithmetic Presentation about Binary Numbers 2015
 
Half Subtractor : Combiational Circuit
Half Subtractor : Combiational CircuitHalf Subtractor : Combiational Circuit
Half Subtractor : Combiational Circuit
 
Binary arithmetic
Binary arithmeticBinary arithmetic
Binary arithmetic
 
RSA NetWitness Log Decoder
RSA NetWitness Log DecoderRSA NetWitness Log Decoder
RSA NetWitness Log Decoder
 
A Model of Social and Cognitive Coherence
A Model of Social and Cognitive CoherenceA Model of Social and Cognitive Coherence
A Model of Social and Cognitive Coherence
 

Similaire à What is a decoder and 2 to 4 DECODER

decoders121-170714184489769876987698749.pptx
decoders121-170714184489769876987698749.pptxdecoders121-170714184489769876987698749.pptx
decoders121-170714184489769876987698749.pptx
tlap4412
 
digital-electronics_9 encoder and decoder pdf
digital-electronics_9 encoder and decoder pdfdigital-electronics_9 encoder and decoder pdf
digital-electronics_9 encoder and decoder pdf
somanathbtech
 
digital-electronics_9 encoder and decoder pdf
digital-electronics_9 encoder and decoder pdfdigital-electronics_9 encoder and decoder pdf
digital-electronics_9 encoder and decoder pdf
somanathbtech
 
DLD Lecture No 22 Decoder Circuit and Types of Decoder.pptx
DLD Lecture No 22 Decoder Circuit and Types of Decoder.pptxDLD Lecture No 22 Decoder Circuit and Types of Decoder.pptx
DLD Lecture No 22 Decoder Circuit and Types of Decoder.pptx
SaveraAyub2
 
combinationalcircuits-161111065011(0).pptx
combinationalcircuits-161111065011(0).pptxcombinationalcircuits-161111065011(0).pptx
combinationalcircuits-161111065011(0).pptx
MmMm633188
 

Similaire à What is a decoder and 2 to 4 DECODER (20)

decoders121-170714184489769876987698749.pptx
decoders121-170714184489769876987698749.pptxdecoders121-170714184489769876987698749.pptx
decoders121-170714184489769876987698749.pptx
 
B sc3 unit 4 combi..lckt
B sc3 unit 4 combi..lcktB sc3 unit 4 combi..lckt
B sc3 unit 4 combi..lckt
 
Combinational Circuits PPT.pdf
Combinational Circuits PPT.pdfCombinational Circuits PPT.pdf
Combinational Circuits PPT.pdf
 
ATT SMK.pptx
ATT SMK.pptxATT SMK.pptx
ATT SMK.pptx
 
digital-electronics_9 encoder and decoder pdf
digital-electronics_9 encoder and decoder pdfdigital-electronics_9 encoder and decoder pdf
digital-electronics_9 encoder and decoder pdf
 
digital-electronics_9 encoder and decoder pdf
digital-electronics_9 encoder and decoder pdfdigital-electronics_9 encoder and decoder pdf
digital-electronics_9 encoder and decoder pdf
 
Decoders
DecodersDecoders
Decoders
 
Combinational Circuits.pptx
Combinational Circuits.pptxCombinational Circuits.pptx
Combinational Circuits.pptx
 
Basic Gates in Digital Logic
Basic Gates in Digital LogicBasic Gates in Digital Logic
Basic Gates in Digital Logic
 
UNIVERSAL PROPERTY.pptx
UNIVERSAL PROPERTY.pptxUNIVERSAL PROPERTY.pptx
UNIVERSAL PROPERTY.pptx
 
STLD-Combinational logic design
STLD-Combinational  logic design STLD-Combinational  logic design
STLD-Combinational logic design
 
Encoder-and-decoder.pptx
Encoder-and-decoder.pptxEncoder-and-decoder.pptx
Encoder-and-decoder.pptx
 
Combinational circuit
Combinational circuitCombinational circuit
Combinational circuit
 
Deld lab manual
Deld lab manualDeld lab manual
Deld lab manual
 
DCF-Combinational circuit
DCF-Combinational circuitDCF-Combinational circuit
DCF-Combinational circuit
 
DLD Lecture No 22 Decoder Circuit and Types of Decoder.pptx
DLD Lecture No 22 Decoder Circuit and Types of Decoder.pptxDLD Lecture No 22 Decoder Circuit and Types of Decoder.pptx
DLD Lecture No 22 Decoder Circuit and Types of Decoder.pptx
 
Encoders
EncodersEncoders
Encoders
 
combinationalcircuits-161111065011(0).pptx
combinationalcircuits-161111065011(0).pptxcombinationalcircuits-161111065011(0).pptx
combinationalcircuits-161111065011(0).pptx
 
Logic Gates.pptx
Logic Gates.pptxLogic Gates.pptx
Logic Gates.pptx
 
Chapter 4 combinational circuit
Chapter 4 combinational circuit Chapter 4 combinational circuit
Chapter 4 combinational circuit
 

Dernier

Dernier (20)

Google Gemini An AI Revolution in Education.pptx
Google Gemini An AI Revolution in Education.pptxGoogle Gemini An AI Revolution in Education.pptx
Google Gemini An AI Revolution in Education.pptx
 
UGC NET Paper 1 Mathematical Reasoning & Aptitude.pdf
UGC NET Paper 1 Mathematical Reasoning & Aptitude.pdfUGC NET Paper 1 Mathematical Reasoning & Aptitude.pdf
UGC NET Paper 1 Mathematical Reasoning & Aptitude.pdf
 
Jamworks pilot and AI at Jisc (20/03/2024)
Jamworks pilot and AI at Jisc (20/03/2024)Jamworks pilot and AI at Jisc (20/03/2024)
Jamworks pilot and AI at Jisc (20/03/2024)
 
2024-NATIONAL-LEARNING-CAMP-AND-OTHER.pptx
2024-NATIONAL-LEARNING-CAMP-AND-OTHER.pptx2024-NATIONAL-LEARNING-CAMP-AND-OTHER.pptx
2024-NATIONAL-LEARNING-CAMP-AND-OTHER.pptx
 
Application orientated numerical on hev.ppt
Application orientated numerical on hev.pptApplication orientated numerical on hev.ppt
Application orientated numerical on hev.ppt
 
HMCS Vancouver Pre-Deployment Brief - May 2024 (Web Version).pptx
HMCS Vancouver Pre-Deployment Brief - May 2024 (Web Version).pptxHMCS Vancouver Pre-Deployment Brief - May 2024 (Web Version).pptx
HMCS Vancouver Pre-Deployment Brief - May 2024 (Web Version).pptx
 
Basic Civil Engineering first year Notes- Chapter 4 Building.pptx
Basic Civil Engineering first year Notes- Chapter 4 Building.pptxBasic Civil Engineering first year Notes- Chapter 4 Building.pptx
Basic Civil Engineering first year Notes- Chapter 4 Building.pptx
 
On National Teacher Day, meet the 2024-25 Kenan Fellows
On National Teacher Day, meet the 2024-25 Kenan FellowsOn National Teacher Day, meet the 2024-25 Kenan Fellows
On National Teacher Day, meet the 2024-25 Kenan Fellows
 
NO1 Top Black Magic Specialist In Lahore Black magic In Pakistan Kala Ilam Ex...
NO1 Top Black Magic Specialist In Lahore Black magic In Pakistan Kala Ilam Ex...NO1 Top Black Magic Specialist In Lahore Black magic In Pakistan Kala Ilam Ex...
NO1 Top Black Magic Specialist In Lahore Black magic In Pakistan Kala Ilam Ex...
 
80 ĐỀ THI THỬ TUYỂN SINH TIẾNG ANH VÀO 10 SỞ GD – ĐT THÀNH PHỐ HỒ CHÍ MINH NĂ...
80 ĐỀ THI THỬ TUYỂN SINH TIẾNG ANH VÀO 10 SỞ GD – ĐT THÀNH PHỐ HỒ CHÍ MINH NĂ...80 ĐỀ THI THỬ TUYỂN SINH TIẾNG ANH VÀO 10 SỞ GD – ĐT THÀNH PHỐ HỒ CHÍ MINH NĂ...
80 ĐỀ THI THỬ TUYỂN SINH TIẾNG ANH VÀO 10 SỞ GD – ĐT THÀNH PHỐ HỒ CHÍ MINH NĂ...
 
Key note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdfKey note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdf
 
Fostering Friendships - Enhancing Social Bonds in the Classroom
Fostering Friendships - Enhancing Social Bonds  in the ClassroomFostering Friendships - Enhancing Social Bonds  in the Classroom
Fostering Friendships - Enhancing Social Bonds in the Classroom
 
Towards a code of practice for AI in AT.pptx
Towards a code of practice for AI in AT.pptxTowards a code of practice for AI in AT.pptx
Towards a code of practice for AI in AT.pptx
 
Plant propagation: Sexual and Asexual propapagation.pptx
Plant propagation: Sexual and Asexual propapagation.pptxPlant propagation: Sexual and Asexual propapagation.pptx
Plant propagation: Sexual and Asexual propapagation.pptx
 
REMIFENTANIL: An Ultra short acting opioid.pptx
REMIFENTANIL: An Ultra short acting opioid.pptxREMIFENTANIL: An Ultra short acting opioid.pptx
REMIFENTANIL: An Ultra short acting opioid.pptx
 
ICT Role in 21st Century Education & its Challenges.pptx
ICT Role in 21st Century Education & its Challenges.pptxICT Role in 21st Century Education & its Challenges.pptx
ICT Role in 21st Century Education & its Challenges.pptx
 
SOC 101 Demonstration of Learning Presentation
SOC 101 Demonstration of Learning PresentationSOC 101 Demonstration of Learning Presentation
SOC 101 Demonstration of Learning Presentation
 
Sensory_Experience_and_Emotional_Resonance_in_Gabriel_Okaras_The_Piano_and_Th...
Sensory_Experience_and_Emotional_Resonance_in_Gabriel_Okaras_The_Piano_and_Th...Sensory_Experience_and_Emotional_Resonance_in_Gabriel_Okaras_The_Piano_and_Th...
Sensory_Experience_and_Emotional_Resonance_in_Gabriel_Okaras_The_Piano_and_Th...
 
COMMUNICATING NEGATIVE NEWS - APPROACHES .pptx
COMMUNICATING NEGATIVE NEWS - APPROACHES .pptxCOMMUNICATING NEGATIVE NEWS - APPROACHES .pptx
COMMUNICATING NEGATIVE NEWS - APPROACHES .pptx
 
TỔNG ÔN TẬP THI VÀO LỚP 10 MÔN TIẾNG ANH NĂM HỌC 2023 - 2024 CÓ ĐÁP ÁN (NGỮ Â...
TỔNG ÔN TẬP THI VÀO LỚP 10 MÔN TIẾNG ANH NĂM HỌC 2023 - 2024 CÓ ĐÁP ÁN (NGỮ Â...TỔNG ÔN TẬP THI VÀO LỚP 10 MÔN TIẾNG ANH NĂM HỌC 2023 - 2024 CÓ ĐÁP ÁN (NGỮ Â...
TỔNG ÔN TẬP THI VÀO LỚP 10 MÔN TIẾNG ANH NĂM HỌC 2023 - 2024 CÓ ĐÁP ÁN (NGỮ Â...
 

What is a decoder and 2 to 4 DECODER

  • 1.
  • 2. BINARY DECODERS • A binary decoder is a multi-input, multi-output combinational circuit that converts a binary code of n input lines into a one out of 2n output code.These are used when there is need to activate exactly one of 2n output based on an n-bit input value. • The figure below shows the general structure of binary decoder in which encoded information is accepted at n input lines and the output is produced at 2n possible output lines.
  • 3. 2 to 4 BINARY DECODER
  • 4. • The figure below shows the truth table for a 2-to-4 decoder. For a given input, the outputsY0 throughY3 are active high if enable input EN is active high (EN = 1).When both inputs A and B are low (or A= B= 0), the outputY0 will be active or High and all other outputs will be low.
  • 5. • From the above truth table we can obtain Boolean expression for the each output as • These expressions can be implemented by using basic logic gates.Thus, the logic circuit design of the 2-to-4 line decoder is given below which is implemented by using NOT and AND gates.Two NOT gates or inverters provide the complement of inputs. • A common enable line is connected to eachAND gate such that when EN= 0 all the outputs are zero and if EN=1, depends on the inputs A and B, outputs are produced. Each output represents one of the minterms of the 2 input variables.
  • 6.
  • 7.
  • 8. • It is also possible to design 2-to-4 decoder using NAND gates as shown in figure below along with truth table.This is constructed with a principle of max terms as outputs.To generate the minterms, we have to use NAND gates which act as inverters. If both inputs are zero (A = B = 0),Y0 will be zero , if A = 0 and B= 1, thenY1 will be 1 and so on. • Therefore, only one output will be low for any combinations of inputs at a given time and all other outputs will be high.This type of decoders is available in IC forms so that 3 to 8, 4 to 16, and 5 to 32 decoders can also be made depends on the application requirement.