This presentation gives an overview of FPGA devices. An FPGA is a device that contains a matrix of re-configurable gate array logic circuitry. When a FPGA is configured, the internal circuitry is connected in a way that creates a hardware implementation of the software application. FPGA devices can deliver the performance and reliability of dedicated hardware circuitry.

1. Introduction to FPGAs
Sudhanshu Janwadkar, TA, ECED

2. Introduction
 An FPGA is a device that contains a matrix of reconfigurable
gate array logic circuitry.
 When a FPGA is configured, the internal circuitry is connected
in a way that creates a hardware implementation of the
software application.
 Unlike hard-wired printed circuit board (PCB) designs which
have fixed hardware resources, FPGA-based systems can
rewire their internal circuitry to allow reconfiguration after the
control system is deployed to the field.
 FPGA devices deliver the performance and reliability of
dedicated hardware circuitry.

3.  Unlike processors, FPGAs use dedicated hardware for
processing logic and do not have an operating system.
 FPGAs are truly parallel in nature so different processing
operations do not have to compete for the same resources. As a
result, the performance of one part of the application is not
affected when additional processing is added.
 Also, multiple control loops can run on a single FPGA device
at different rates.
 A single FPGA can replace thousands of discrete components
by incorporating millions of logic gates in a single integrated
circuit (IC) chip.
Introduction

4. Why FPGA?
Digital Logic

5. Digital Logic Meant:
 Fixed hardware = Fixed usability
 Limited flexibility only possible by adding software support,
for example processors
 Upgrade or alteration in hardware logic was not guaranteed
 An upgrade meant a completely new system
Why FPGA?

6. Why FPGA?
Programmable Logic

7. Why FPGA?
 PROM
 The first type of user-programmable chip that could implement
logic circuits was the Programmable Read-Only Memory
(PROM), in which address lines can be used as logic circuit
inputs and data lines as outputs.
Drawbacks:
 Logic functions require more than a few product terms
 A PROM requires a full decoder for its address inputs.
 PROMS are thus an inefficient architecture for realizing logic
circuits -> Hence, they are rarely used in practice for that
purpose.

8. Why FPGA?
PLAs
 Came as Replacement to PROMs
 Logically, a PLA is a circuit that allows
implementing Boolean functions in sum-of-
product form.
 The typical implementation consists of input
buffers for all inputs, the programmable AND-
matrix followed by the programmable OR-
matrix, and output buffers.
 The input buffers provide both the original and
the inverted values of each PLA input. The
input lines run horizontally into the AND
matrix, while the so-called product-term lines
run vertically.

9. PLA Drawbacks:
 Expensive to manufacture
 offer poor speed-performance.
 Both disadvantages are due to the two levels of configurable
logic, because programmable logic planes are difficult to
manufacture and introduce significant propagation delays.

10. Why FPGA?
 PALs
 To overcome the weaknesses of PAL, Programmable Array
Logic (PAL) devices were developed.
 PALs provide only a single level of programmability,
consisting of a programmable “wired” AND plane that feeds
fixed OR-gates.

11. Why FPGA?
How FPGA is different over PLA and PALs?
 FPGA provides its user a way to configure:
 1. The intersection between the logic blocks and
 2. The function of each logic block.

12. Architecture

13. Note: Figure Intended Only for Understanding of the Concept
Architecture

14.  The internal resources of an FPGA chip consist of a matrix of
configurable logic blocks (CLBs) surrounded by a periphery of
I/O blocks
 Signals are routed within the FPGA matrix by programmable
interconnect switches and wire routes.
Architecture

15. Architecture: Logic Blocks
 Logic block of an FPGA can be configured in such a way
that it can provide functionality as simple as that of
transistor or as complex as that of a microprocessor.
 It can used to implement different combinations of
combinational and sequential logic functions.
 Logic blocks of an FPGA can be implemented by any of
the following:
1. 3. n-input Lookup tables
2. Multiplexers
3. Flip-Flops
4. Buffers

16. Architecture: Interconnects
 Routing in FPGAs consists of wire segments of varying lengths
which can be interconnected via electrically programmable
switches.
 Density of logic block used in an FPGA depends on length and
number of wire segments used for routing.
 Number of segments used for interconnection typically is a
trade-off between density of logic blocks used and amount of
area used up for routing.

17. Simplified Architecture

18. FPGA Structural Classification
 Basic structure of an FPGA includes Logic elements,
Programmable interconnects and Memory.
 Arrangement of these blocks is specific to particular
manufacturer.
 On the basis of internal arrangement of blocks FPGAs can be
divided into three classes:
 Symmetrical arrays
 Row based architecture
 Hierarchical PLDs

19. Symmetrical arrays

20. Symmetrical arrays
 This architecture consists of logic elements (called CLBs)
arranged in rows and columns of a matrix and interconnect laid
out between.
 This symmetrical matrix is surrounded by I/O blocks which
connect it to outside world. I/O blocks also control functions
such as tri-state control, output transition speed.
 Each CLB consists of n-input Lookup table and a pair of
programmable flip flops.
 Interconnects provide routing path. Direct interconnects
between adjacent logic elements result smaller delay compared
to general purpose interconnect.

21. Row based Architecture

22. Row based Architecture
 Row based architecture consists of alternating rows of logic
modules and programmable interconnect tracks.
 I/O blocks is located in the periphery of the rows.
 One row may be connected to adjacent rows via vertical
interconnect.
 Logic modules can be implemented in various combinations.
 Combinatorial modules contain only combinational elements
while Sequential modules contain both combinational elements
along with flip flops. Thus, sequential module can implement
complex combinatorial-sequential functions.

23. Hierarchical PLDs

24. Hierarchical PLDs
 This architecture is designed in hierarchical manner with top
level containing only logic blocks and interconnects.
 Each logic block contains number of logic modules. And each
logic module has combinatorial as well as sequential functional
elements.
 Communication between logic blocks is achieved by
programmable interconnect arrays.
 Input output blocks surround this scheme of logic blocks and
interconnects.

25. FPGA Classification on user programmable
switch technologies
So far We have understood that,
 FPGAs are based on an array of logic modules and a supply of
uncommitted wires to route signals.
 In gate arrays these wires are connected by a mask design
during manufacture.
 In FPGAs, however, these wires are connected by the user and
therefore must use an electronic device to connect them.

26.  Three types of devices based on how interconnects are
configured:
 Pass transistors controlled by an SRAM cell,
 Flash or EEPROM cell to pass the signal,
 Direct connect using anti-fuses.
FPGA Classification on User
Programmable Switch technologies

27. SRAM Based FPGA

28.  SRAM cells find two applications in FPGA:
 for controlling the gate nodes of pass-transistor switches
and
 to control the select lines of multiplexers that drive logic
block inputs.
 Whether an FPGA uses pass-transistors or multiplexers or both
depends on the particular product.
SRAM Based FPGA

29. Advantages:
 The major advantage of SRAM based FPGA is that they are
infinitely re-programmable.
 The function can be changed quickly by merely changing the
contents of a PROM (External Memory to store program).
 The function can be updated on-field, the field by uploading
new application code, a feature attractive to designers.
Disadvantages:
 It does result in large number of interconnects. The
interconnect elements have high impedance and capacitance
and consume more area than other technologies.
 They need to be reprogrammed each time when power is
applied
 They need an external memory to store program
SRAM Based FPGA

30. Antifuse Based FPGA

31. Antifuse Based FPGA
 An antifuse is positioned between two interconnect wires and
physically consists of three sandwiched layers: the top and
bottom layers are conductors, and the middle layer is an
insulator.
 When un-programmed, the insulator isolates the top and
bottom layers, but when programmed the insulator changes to
become a low-resistance link. It uses Poly-Si and n+ diffusion
as conductors and ONO as an insulator

32. Advantages:
 The antifuse based cell is the highest density interconnect by
being a true cross point. Thus the designer has a much larger
number of interconnects so logic modules can be smaller
and more efficient.
 Placement and routing requires much lesser time.
 The Antifuse has an inherently low capacitance and
resistance such that the fastest parts are all Antifuse based.
Disadvantages:
 These devices however are only one-time programmable
and therefore have to be thrown out every time a change is
made in the design.
 Requirement to integrate the fabrication of the antifuses into
the IC process
Antifuse Based FPGA

33. EEPROM Based FPGA
 The EEPROM/FLASH cell in FPGAs can be used in two ways,
as a control device as in an SRAM cell or as a directly
programmable switch.
Advantages:
 They are non-volatile so they do not require an extra PROM
for loading.
Disadvantages:
 The EEPROM process is complicated.

34. FPGA Design Flow

35.  1. System Design
At this stage designer has to decide what portion of his
functionality has to be implemented on FPGA and how to
integrate that functionality with rest of the system.
 2. Design Entry
 The option of Schematic capture is more or less ruled out,
designs have become more
 Designer describes design functionality by using one of the
various Hardware Description Languages (HDLs) like Gezel,
Verilog or VHDL.
FPGA Design Flow

36.  3. Simulation
 Functional simulation.
 A simulator is used to execute the design and confirm that
the correct outputs are produced for a given set of test inputs.
 Although problems with the size or timing of the hardware
may appear later, the designer can at least be sure that his
logic is functionally correct before going on to the next stage
of development.
FPGA Design Flow

37.  4. Synthesis
 First, an intermediate representation of the hardware design is
produced. This step is called synthesis and the result is a
representation called a Netlist.
 The Netlist is device independent, so its contents do not
depend on the particulars of the FPGA or CPLD; it is usually
stored in a standard format called the Electronic Design
Interchange Format (EDIF).
FPGA Design Flow

38.  5. Place and Route
 This step involves mapping the logical structures described
in the netlist onto actual macrocells, interconnections, and
input and output pins. The result of the place & route
process is a bitstream.
 Each CPLD or FPGA (or family) has its own, bitstream
format.
 We can say that the bitstream is the binary data that must be
loaded into the FPGA or CPLD to cause that chip to
execute a particular hardware design.
FPGA Design Flow

39.  6. Design Verification
 Bit stream file is fed to a simulator which simulates the
design functionality and reports errors in desired behavior of
the design.
 Later the design is loading onto the target FPGA device and
testing is done in real environment.
FPGA Design Flow

40. Hardware Design V/S Software Design
 A description of the hardware's structure and behaviour is
written in a high-level hardware description language (usually
VHDL or Verilog) and that code is then compiled and
downloaded prior to execution.
 In Software Development, the logic is implemented using
coding languages. In Embedded applications, firmware is
written using Embedded C etc
 The most striking difference between hardware and software
design is the way a developer must think about the problem.

41.  Software developers tend to think sequentially, even when they
are developing a multi-threaded application. The lines of
source code that they write are always executed in that order, at
least within a given thread
 During design entry, hardware designers must think and
program in parallel. All of the input signals are processed in
parallel, as they travel through a set of execution engines-each
one a series of macrocells and interconnections-toward their
destination output signals. Therefore, the statements of a
hardware description language create structures, all of which
are "executed" at the very same time.
Hardware Design V/S Software Design

42. Dualism of Hardware and Software Design

43. Design Paradigm
 In a hardware model, circuit elements operate in parallel. Thus,
by using more circuit elements, more work can be done within
a single clock cycle.
 Software executes instructions sequentially. By using more
instructions, a software program will take more time to
complete.
 Thus, a hardware designer solves problems by dividing
complex design into simpler hardware blocks (called
decomposition in space), while a software designer solves
problems by dividing it to simpler software sub-routines (called
decomposition in time)
 Relate wrt FPGA??

44. Resource Cost
 Decomposition in space, as used by a hardware designer,
means that more gates are required for when a more complex
design needs to be implemented.
 Decomposition in time, as used by a software designer, implies
that a more complex design will take more instructions to
complete.
 Therefore, the resource cost for hardware is circuit area, while
the resource cost for software is execution time.
 Relate wrt FPGA??

45. Design Constraints
 A hardware designer is constrained by the clock cycle period of
a design. A software designer, on the other hand, is limited by
the memory space available with the processor.
 Thus, the design constraints for hardware are in terms of a time
budget, while the design constraints for software are fixed by
the memory space of CPU.
 Relate wrt FPGA??

46. Flexibility
 Flexibility is the ease by which the application can be modified
or adapted after the target architecture for that application is
manufactured.
 In software, flexibility is essentially free. In hardware on the
other hand, flexibility is not freely available. Hardware
flexibility requires circuit elements that can be easily reused for
different activities or functions in a design.
 Software excels over hardware in the support of application
flexibility.
 Relate wrt FPGA??

47. Parallelism
 Parallelism is the most obvious approach to improving
performance.
 For hardware, parallelism comes for free as part of the design
paradigm.
 For software, on the other hand, parallelism is a major
challenge. A truly parallel software implementation can be
made only if multiple processors are available, but inter-
processor communication and synchronization become a
challenge.
 Relate wrt FPGA??

48. Modelling
 In software, modelling and implementation are very close.
Indeed, when a designer writes a C program, the compilation of
that program for the appropriate target processor will also
result in the implementation of the program!
 In hardware, the model and the implementation of a design are
distinct concepts.
 Relate wrt FPGA??

49. Reuse
 The idea of reuse is that a component of a larger circuit or a
program can be later reused in the context of a different design.
 In software, re-use is quite popular. When designing a
complex program these days, designers will start from a set of
standard libraries that are well-documented.
 For hardware design, re-use is not yet popular. Some IP cores
are available for FPGAs.
 Relate wrt FPGA??

50. References
 Design of Embedded Processors , Module 4, IIT-KGP NPTEL
 A Practical Introduction to Hardware/Software Codesign-book
by Patrick Schaumont

51. Additional Video Resources
 https://www.youtube.com/watch?v=gUsHwi4M4xE
 https://www.youtube.com/watch?v=CLUoWkJUnN0