objectif général : comprendre comment l'ordinateur communique avec son environnement
objectifs spécifiques :
- connaître le rôle et la composition de l'interface d'entrée et sortie
- comprendre la scrutation ou interrogation
- comprendre les requêtes d'interruption
- comprendre l'accès direct à la mémoire ou DMA
- connaître le fonctionnement des bus
- connaître les types de liaison
objectif général : comprendre comment l'ordinateur communique avec son environnement
objectifs spécifiques :
- connaître le rôle et la composition de l'interface d'entrée et sortie
- comprendre la scrutation ou interrogation
- comprendre les requêtes d'interruption
- comprendre l'accès direct à la mémoire ou DMA
- connaître le fonctionnement des bus
- connaître les types de liaison
The document provides instructions for various commands used in the Baseband 6630 Moshell interface. It describes how to check the status of cells and sectors, save and check configuration versions, restart the baseband, list radio ports, antenna units, and installed equipment. It also provides examples for checking IP addresses, VLAN configurations, and pinging an IP address.
The document discusses Ericsson radio network equipment used in Mumbai, India including:
1. An Ericsson baseband unit (BBU 6630) and radio unit (RBS AIR 6468) that support 5G, LTE, and legacy radio technologies.
2. The BBU facilitates a scalable system with indoor baseband units and external radios.
3. The RBS is an advanced antenna system capable of beamforming and massive MIMO to enhance coverage, capacity, and performance.
4. Additional modules like the capacity plug-in unit, radio modules, and fiber distribution unit that integrate with the system are also described.
This document provides an overview of IP troubleshooting for LTE networks. It describes the key network elements in an EPS including the eNodeB, MME, SGW, PGW, PCRF and HSS. It explains the functionality of each element. The document also discusses transport network configuration, security, and backhaul recommendations for LTE networks.
OAM 3G Network Ericsson discusses operation and maintenance of Ericsson's 3G radio access network. Session 1 covers the OSS, EMAS and other tools used for network operation. Session 2 discusses commissioning radio base stations, replacing modules, backing up network nodes, and upgrading base station capacity. Key tools include OSS, EMAS, element manager and scripts for configuration tasks. Proper planning, tools and procedures are needed for tasks like commissioning, module replacement, backups and hardware upgrades.
Mobile data traffic is growing exponentially due to increased mobile internet usage. LTE was developed as the next step to address this growth by providing significantly higher data rates, lower latency, and improved system capacity over 3G networks. LTE uses OFDMA for downlinks and SC-FDMA for uplinks to achieve higher spectrum efficiency. It supports bandwidths from 1.4MHz up to 20MHz and can operate in paired and unpaired spectrum. The LTE architecture separates the radio access network and core network functions.
The document discusses the evolution of mobile networks from 3G to 4G and 5G, and provides an overview of SKY Network's plan to modernize its radio access network (RAN). The modernization will involve deploying 4G and 5G radio nodes across different scenarios, including replacing existing 3G nodes with 4G/5G, deploying new 4G-only nodes, and using indoor small cells. The interfaces, architectures and equipment involved are also described at a high level.
This document discusses Ericsson's 5G cooperation and knowledge sharing sessions with Etisalat. It provides details on Ericsson's network solutions for a non-standalone 5G deployment, including the use of a gNB, eNB, router, and synchronization components. Diagrams show example network topologies. Technical specifications are given for the AIR 6488 antenna, Baseband 6630, and Router 6471.
This document provides instructions for integrating a baseband 521x into an OSS RC, RNC, BSC network. It describes the various configuration types for new and existing sites. The procedure includes preparing tools and software, installing hardware, integrating the baseband into the RNC and OSS, setting licenses, and configuring primary/secondary and external alarm settings. It aims to commission and integrate the baseband while following standard processes.
The document discusses the structure and design flow of FPGAs. It describes how HDL code is synthesized to FPGA primitives which are then mapped and placed onto configurable logic blocks and routed. It discusses the components within configurable logic blocks including lookup tables (LUTs), multiplexers, and flip flops. It provides examples of optimizing logic using these resources such as implementing adders and multiplexers more efficiently.
This document provides an overview of Dense Wavelength Division Multiplexing (DWDM) technology. It discusses the concepts of fiber optics, wavelength division multiplexing, bandwidth demand over time, and options for increasing bandwidth capacity such as TDM and WDM. It also describes DWDM components like transponders, multiplexers/demultiplexers, optical add/drop multiplexers, and erbium-doped fiber amplifiers. Finally, it discusses the evolution of DWDM technology and its benefits for optical networking.
This document provides an overview and copyright information for the book "Verilog HDL Design Examples" by Joseph Cavanagh. It includes the following key details:
- The book contains Verilog design examples for logic design using Verilog HDL.
- CRC Press is publishing the book as an imprint of the Taylor & Francis Group.
- Copyright ownership is held by Taylor & Francis Group, LLC and no claim is made to original U.S. government works.
- The book is intended to provide reliable design information and examples to readers.
The document provides examples of various VHDL constructs including entity declarations, architecture bodies, components, signals, constants, data types and objects. It shows how to describe synchronous and asynchronous logic using processes, and how to translate a state flow diagram to a two-process finite state machine description. Key constructs demonstrated include entity and architecture declarations, port maps, processes, if/else statements, case statements and sequential signal assignments.
This document discusses digital system design topics including tristate buffers, read-only memories (ROMs), and programmable logic devices. It covers how tristate buffers can output high, low, or high-impedance signals. ROMs are introduced as memory devices that can only be written once but read many times. Programmable logic arrays (PLAs) and programmable array logic (PALs) implement logic functions using a sum-of-products expression. More complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs) allow many logic functions to be programmed on a single chip.
The document discusses reconfigurable computing architectures and FPGA internals. It covers two main types of reconfigurable computing - microprocessor-based using dynamically joined multi-core processors, and FPGA-based using programmable logic blocks connected to processors. The internals of FPGAs are described including lookup tables, logic blocks, and configurable logic blocks. Performance evaluation considers mapping designs to logic blocks and calculating timing.
The document provides instructions for various commands used in the Baseband 6630 Moshell interface. It describes how to check the status of cells and sectors, save and check configuration versions, restart the baseband, list radio ports, antenna units, and installed equipment. It also provides examples for checking IP addresses, VLAN configurations, and pinging an IP address.
The document discusses Ericsson radio network equipment used in Mumbai, India including:
1. An Ericsson baseband unit (BBU 6630) and radio unit (RBS AIR 6468) that support 5G, LTE, and legacy radio technologies.
2. The BBU facilitates a scalable system with indoor baseband units and external radios.
3. The RBS is an advanced antenna system capable of beamforming and massive MIMO to enhance coverage, capacity, and performance.
4. Additional modules like the capacity plug-in unit, radio modules, and fiber distribution unit that integrate with the system are also described.
This document provides an overview of IP troubleshooting for LTE networks. It describes the key network elements in an EPS including the eNodeB, MME, SGW, PGW, PCRF and HSS. It explains the functionality of each element. The document also discusses transport network configuration, security, and backhaul recommendations for LTE networks.
OAM 3G Network Ericsson discusses operation and maintenance of Ericsson's 3G radio access network. Session 1 covers the OSS, EMAS and other tools used for network operation. Session 2 discusses commissioning radio base stations, replacing modules, backing up network nodes, and upgrading base station capacity. Key tools include OSS, EMAS, element manager and scripts for configuration tasks. Proper planning, tools and procedures are needed for tasks like commissioning, module replacement, backups and hardware upgrades.
Mobile data traffic is growing exponentially due to increased mobile internet usage. LTE was developed as the next step to address this growth by providing significantly higher data rates, lower latency, and improved system capacity over 3G networks. LTE uses OFDMA for downlinks and SC-FDMA for uplinks to achieve higher spectrum efficiency. It supports bandwidths from 1.4MHz up to 20MHz and can operate in paired and unpaired spectrum. The LTE architecture separates the radio access network and core network functions.
The document discusses the evolution of mobile networks from 3G to 4G and 5G, and provides an overview of SKY Network's plan to modernize its radio access network (RAN). The modernization will involve deploying 4G and 5G radio nodes across different scenarios, including replacing existing 3G nodes with 4G/5G, deploying new 4G-only nodes, and using indoor small cells. The interfaces, architectures and equipment involved are also described at a high level.
This document discusses Ericsson's 5G cooperation and knowledge sharing sessions with Etisalat. It provides details on Ericsson's network solutions for a non-standalone 5G deployment, including the use of a gNB, eNB, router, and synchronization components. Diagrams show example network topologies. Technical specifications are given for the AIR 6488 antenna, Baseband 6630, and Router 6471.
This document provides instructions for integrating a baseband 521x into an OSS RC, RNC, BSC network. It describes the various configuration types for new and existing sites. The procedure includes preparing tools and software, installing hardware, integrating the baseband into the RNC and OSS, setting licenses, and configuring primary/secondary and external alarm settings. It aims to commission and integrate the baseband while following standard processes.
The document discusses the structure and design flow of FPGAs. It describes how HDL code is synthesized to FPGA primitives which are then mapped and placed onto configurable logic blocks and routed. It discusses the components within configurable logic blocks including lookup tables (LUTs), multiplexers, and flip flops. It provides examples of optimizing logic using these resources such as implementing adders and multiplexers more efficiently.
This document provides an overview of Dense Wavelength Division Multiplexing (DWDM) technology. It discusses the concepts of fiber optics, wavelength division multiplexing, bandwidth demand over time, and options for increasing bandwidth capacity such as TDM and WDM. It also describes DWDM components like transponders, multiplexers/demultiplexers, optical add/drop multiplexers, and erbium-doped fiber amplifiers. Finally, it discusses the evolution of DWDM technology and its benefits for optical networking.
This document provides an overview and copyright information for the book "Verilog HDL Design Examples" by Joseph Cavanagh. It includes the following key details:
- The book contains Verilog design examples for logic design using Verilog HDL.
- CRC Press is publishing the book as an imprint of the Taylor & Francis Group.
- Copyright ownership is held by Taylor & Francis Group, LLC and no claim is made to original U.S. government works.
- The book is intended to provide reliable design information and examples to readers.
The document provides examples of various VHDL constructs including entity declarations, architecture bodies, components, signals, constants, data types and objects. It shows how to describe synchronous and asynchronous logic using processes, and how to translate a state flow diagram to a two-process finite state machine description. Key constructs demonstrated include entity and architecture declarations, port maps, processes, if/else statements, case statements and sequential signal assignments.
This document discusses digital system design topics including tristate buffers, read-only memories (ROMs), and programmable logic devices. It covers how tristate buffers can output high, low, or high-impedance signals. ROMs are introduced as memory devices that can only be written once but read many times. Programmable logic arrays (PLAs) and programmable array logic (PALs) implement logic functions using a sum-of-products expression. More complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs) allow many logic functions to be programmed on a single chip.
The document discusses reconfigurable computing architectures and FPGA internals. It covers two main types of reconfigurable computing - microprocessor-based using dynamically joined multi-core processors, and FPGA-based using programmable logic blocks connected to processors. The internals of FPGAs are described including lookup tables, logic blocks, and configurable logic blocks. Performance evaluation considers mapping designs to logic blocks and calculating timing.
4. Le Module d’échange
Dialoguer avec
l'extérieur
• E-S TOR
• E-S Communication
• Timers : compter,
gérer le temps
• E-S analogiques
5. Le Processeur
• Maître du bus
• Initialisation « Reset » :
le µP charge le
vecteur de RESET
• µP a besoin
d ’énergie et d ’une
horloge
6. Le bloc Mémoire
• Mémoire Mortes:
Lire des données
• Mémoire Vive :
Écrire et Lire des
Données
• Le Vecteur de Reset
et le Boot en
Mémoire Morte
7. Décodage adresse
Le µP gère un
ensemble de
positions mémoires
Il faut positionner les
composants dans
l’espace Mémoire
Le Décodage
d ’adresse élabore
les « CS » des
composants
0000 h
FFFFh
64 Ko Composant
@ Début
Taille
8. Exemple
• µP 16 lignes @
• Composant 1 : 14 bornes @
• Composant 2 : 15 bornes @
Pour qu’un composant soit
sélection, il faut CS=0
Composant 1 : il faut A15=0 et
A14=0
Composant 2 : il faut A15=1
Pour accéder au premier
registre d ’un composant, il
faut :
CS=0
et la valeur «0» sur les bornes
@ du composant
/CS
/CS
OU
A14
A15
A15
=1
15
14 16
Comp 1
Comp 2
9. Espace
mémoire
du µP
64 Ko
Plan Mémoire
@ début composant 1
A15 à A14 «0» et A13 à A0 à «0»
- 0000 h
@ début composant 2
A15 «1» et A14 à A0 à «0»
- 8000h
@ fin composant 1
A15 à A14 «0» et A13 à A0 à «1»
- 3FFFh
@ fin composant 2
A15 «1» et A14 à A0 à «1»
- FFFFh
0000h
Composant 1
3FFFh
FFFFh
Composant 2
8000h
Plan Mémoire